The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
임베디드 시스템의 시각적 개체 감지에는 전력 소비, 처리 성능 및 감지 정확도 간의 균형이 존재하는 다중 목표 최적화 문제가 포함됩니다. 높은 처리 성능과 낮은 전력 소비를 갖춘 새로운 Pareto 솔루션을 위해 본 논문에서는 다중 채널 기능을 사용하는 의사결정 트리 앙상블을 위한 하드웨어 아키텍처를 제안합니다. 효율적인 검출을 위해 제안된 아키텍처는 이미지 공간의 병렬성 외에도 특징 채널의 차원성을 활용하고 충돌 없이 임의 메모리 액세스를 달성하기 위해 작업 스케줄링을 채택합니다. 평가 결과에 따르면 보행자 감지 기능을 통합한 제안된 아키텍처를 FPGA로 구현하면 상대적으로 적은 양의 리소스가 필요하면서도 229MHz 작동 주파수에서 초당 100억 350만 샘플을 처리할 수 있는 것으로 나타났습니다. 결과적으로 제안된 아키텍처는 1080P Full HD 이미지에 대해 XNUMXfps 처리 성능을 달성하고 임베디드 시스템용으로 개발된 기존 객체 감지 하드웨어 아키텍처보다 성능이 뛰어납니다.
Koichi MITSUNARI
Osaka University
Jaehoon YU
Osaka University
Takao ONOYE
Osaka University
Masanori HASHIMOTO
Osaka University
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Koichi MITSUNARI, Jaehoon YU, Takao ONOYE, Masanori HASHIMOTO, "Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 9, pp. 1298-1307, September 2018, doi: 10.1587/transfun.E101.A.1298.
Abstract: Visual object detection on embedded systems involves a multi-objective optimization problem in the presence of trade-offs between power consumption, processing performance, and detection accuracy. For a new Pareto solution with high processing performance and low power consumption, this paper proposes a hardware architecture for decision tree ensemble using multiple channels of features. For efficient detection, the proposed architecture utilizes the dimensionality of feature channels in addition to parallelism in image space and adopts task scheduling to attain random memory access without conflict. Evaluation results show that an FPGA implementation of the proposed architecture with an aggregated channel features pedestrian detector can process 229 million samples per second at 100MHz operation frequency while it requires a relatively small amount of resources. Consequently, the proposed architecture achieves 350fps processing performance for 1080P Full HD images and outperforms conventional object detection hardware architectures developed for embedded systems.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.1298/_p
부
@ARTICLE{e101-a_9_1298,
author={Koichi MITSUNARI, Jaehoon YU, Takao ONOYE, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble},
year={2018},
volume={E101-A},
number={9},
pages={1298-1307},
abstract={Visual object detection on embedded systems involves a multi-objective optimization problem in the presence of trade-offs between power consumption, processing performance, and detection accuracy. For a new Pareto solution with high processing performance and low power consumption, this paper proposes a hardware architecture for decision tree ensemble using multiple channels of features. For efficient detection, the proposed architecture utilizes the dimensionality of feature channels in addition to parallelism in image space and adopts task scheduling to attain random memory access without conflict. Evaluation results show that an FPGA implementation of the proposed architecture with an aggregated channel features pedestrian detector can process 229 million samples per second at 100MHz operation frequency while it requires a relatively small amount of resources. Consequently, the proposed architecture achieves 350fps processing performance for 1080P Full HD images and outperforms conventional object detection hardware architectures developed for embedded systems.},
keywords={},
doi={10.1587/transfun.E101.A.1298},
ISSN={1745-1337},
month={September},}
부
TY - JOUR
TI - Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1298
EP - 1307
AU - Koichi MITSUNARI
AU - Jaehoon YU
AU - Takao ONOYE
AU - Masanori HASHIMOTO
PY - 2018
DO - 10.1587/transfun.E101.A.1298
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2018
AB - Visual object detection on embedded systems involves a multi-objective optimization problem in the presence of trade-offs between power consumption, processing performance, and detection accuracy. For a new Pareto solution with high processing performance and low power consumption, this paper proposes a hardware architecture for decision tree ensemble using multiple channels of features. For efficient detection, the proposed architecture utilizes the dimensionality of feature channels in addition to parallelism in image space and adopts task scheduling to attain random memory access without conflict. Evaluation results show that an FPGA implementation of the proposed architecture with an aggregated channel features pedestrian detector can process 229 million samples per second at 100MHz operation frequency while it requires a relatively small amount of resources. Consequently, the proposed architecture achieves 350fps processing performance for 1080P Full HD images and outperforms conventional object detection hardware architectures developed for embedded systems.
ER -