The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 회귀 분석을 사용하여 공정 변화를 인식하는 DFF(D-Flip-Flop) 설계 방법론을 설명합니다. 우리는 프로세스 변화 하에서 DFF의 최악의 지연 특성을 모델링하기 위해 회귀 분석을 사용할 것을 제안합니다. 최악의 경우 지연 성능을 개선하기 위해 DFF의 트랜지스터 폭 조정에 대한 회귀 방정식을 활용합니다. 회귀 분석은 DFF 내부의 성능에 중요한 트랜지스터를 식별할 수 있을 뿐만 아니라 DFF 지연 성능에 대한 이러한 영향을 정량적 형태로 보여줍니다. 제안된 설계 방법론은 몬테카를로 시뮬레이션을 통해 검증된다. 결과는 제안한 방법이 숙련된 셀 설계자가 설계한 DFF와 비교하여 유사하거나 더 나은 지연 특성을 갖는 DFF를 설계하는 데 성공했음을 보여줍니다.
Shinichi NISHIZAWA
Saitama University
Hidetoshi ONODERA
Kyoto University
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Shinichi NISHIZAWA, Hidetoshi ONODERA, "Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 12, pp. 2222-2230, December 2018, doi: 10.1587/transfun.E101.A.2222.
Abstract: This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.2222/_p
부
@ARTICLE{e101-a_12_2222,
author={Shinichi NISHIZAWA, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis},
year={2018},
volume={E101-A},
number={12},
pages={2222-2230},
abstract={This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.},
keywords={},
doi={10.1587/transfun.E101.A.2222},
ISSN={1745-1337},
month={December},}
부
TY - JOUR
TI - Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2222
EP - 2230
AU - Shinichi NISHIZAWA
AU - Hidetoshi ONODERA
PY - 2018
DO - 10.1587/transfun.E101.A.2222
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2018
AB - This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.
ER -