The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
반도체 소자 제조 기술이 집적도가 높아지고 형상 크기가 작아짐에 따라 설계 단계에서 추정된 결함 수준과 제조된 소자에 대해 보고된 결함 수준 간의 격차가 더 넓어지고 테스트 비용과 부품 제조 비용을 포함한 전체 제조 비용을 통제하기가 더욱 어려워졌습니다. 현장실패. 결함 발생 확률을 고려하여 보다 정확한 결함 커버리지를 추정하기 위해, 각 결함에 해당하는 임계 영역을 기반으로 가중 결함 커버리지 추정을 제안했습니다. 이전에는 다양한 결함 모델이 별도로 처리되었습니다. 따라서 패턴 압축 효율성과 런타임이 최적화되지 않았습니다. 본 연구에서는 가중치 브리지와 개방형 결함 커버리지를 통합적으로 고려한 빠른 테스트 패턴 생성 기법을 제안한다. 제안 기법은 2단계 테스트 패턴 생성을 적용하는데, 두 번째 단계에서 생성된 교량 결함만을 대상으로 하는 테스트 패턴은 고정된 크기의 검색 창으로 재정렬되어 다음을 달성합니다. O(n) 계산 복잡성. 실험 결과는 초기 목표 결함 크기의 10%와 고정된 작은 창 크기를 사용하여 제안된 방식이 단순한 그리디 기반 재정렬과 비교할 때 약 100%의 패턴 수 증가 대신 약 5배의 런타임 단축을 달성한다는 것을 나타냅니다.
Masayuki ARAI
Nihon University
Shingo INUYAMA
Tokyo Metropolitan University
Kazuhiko IWASAKI
Tokyo Metropolitan University
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부
Masayuki ARAI, Shingo INUYAMA, Kazuhiko IWASAKI, "Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 12, pp. 2262-2270, December 2018, doi: 10.1587/transfun.E101.A.2262.
Abstract: As semiconductor device manufacturing technology evolves toward higher integration and reduced feature size, the gap between the defect level estimated at the design stage and that reported for fabricated devices has become wider, making it more difficult to control total manufacturing cost including test cost and cost for field failure. To estimate fault coverage more precisely considering occurrence probabilities of faults, we have proposed weighted fault coverage estimation based on critical area corresponding to each fault. Previously different fault models were handled separately; thus, pattern compression efficiency and runtime were not optimized. In this study, we propose a fast test pattern generation scheme that considers weighted bridge and open fault coverage in an integrated manner. The proposed scheme applies two-step test pattern generation, wherein test patterns generated at second step that target only bridge faults are reordered with a search window of fixed size, achieving O(n) computational complexity. Experimental results indicate that with 10% of the initial target fault size and a fixed, small window size, the proposed scheme achieves approximately 100 times runtime reduction when compared to simple greedy-based reordering, in exchange for about 5% pattern count increment.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.2262/_p
부
@ARTICLE{e101-a_12_2262,
author={Masayuki ARAI, Shingo INUYAMA, Kazuhiko IWASAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering},
year={2018},
volume={E101-A},
number={12},
pages={2262-2270},
abstract={As semiconductor device manufacturing technology evolves toward higher integration and reduced feature size, the gap between the defect level estimated at the design stage and that reported for fabricated devices has become wider, making it more difficult to control total manufacturing cost including test cost and cost for field failure. To estimate fault coverage more precisely considering occurrence probabilities of faults, we have proposed weighted fault coverage estimation based on critical area corresponding to each fault. Previously different fault models were handled separately; thus, pattern compression efficiency and runtime were not optimized. In this study, we propose a fast test pattern generation scheme that considers weighted bridge and open fault coverage in an integrated manner. The proposed scheme applies two-step test pattern generation, wherein test patterns generated at second step that target only bridge faults are reordered with a search window of fixed size, achieving O(n) computational complexity. Experimental results indicate that with 10% of the initial target fault size and a fixed, small window size, the proposed scheme achieves approximately 100 times runtime reduction when compared to simple greedy-based reordering, in exchange for about 5% pattern count increment.},
keywords={},
doi={10.1587/transfun.E101.A.2262},
ISSN={1745-1337},
month={December},}
부
TY - JOUR
TI - Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2262
EP - 2270
AU - Masayuki ARAI
AU - Shingo INUYAMA
AU - Kazuhiko IWASAKI
PY - 2018
DO - 10.1587/transfun.E101.A.2262
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2018
AB - As semiconductor device manufacturing technology evolves toward higher integration and reduced feature size, the gap between the defect level estimated at the design stage and that reported for fabricated devices has become wider, making it more difficult to control total manufacturing cost including test cost and cost for field failure. To estimate fault coverage more precisely considering occurrence probabilities of faults, we have proposed weighted fault coverage estimation based on critical area corresponding to each fault. Previously different fault models were handled separately; thus, pattern compression efficiency and runtime were not optimized. In this study, we propose a fast test pattern generation scheme that considers weighted bridge and open fault coverage in an integrated manner. The proposed scheme applies two-step test pattern generation, wherein test patterns generated at second step that target only bridge faults are reordered with a search window of fixed size, achieving O(n) computational complexity. Experimental results indicate that with 10% of the initial target fault size and a fixed, small window size, the proposed scheme achieves approximately 100 times runtime reduction when compared to simple greedy-based reordering, in exchange for about 5% pattern count increment.
ER -