The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
첨단 기술 노드의 집적 회로 설계에서 레이아웃 밀도 균일성은 CMP 가변성으로 인해 제조 가능성에 큰 영향을 미칩니다. 특히 아날로그 설계에서는 유용한 도구가 거의 없기 때문에 설계자들은 밀도 검사를 통과하는 데 어려움을 겪고 있습니다. 이 문제를 해결하기 위해 우리는 트랜지스터 어레이(TA) 스타일의 아날로그 레이아웃에 중점을 두고 복잡한 설계 규칙에 부합하는 밀도 최적화 알고리즘을 제안합니다. TA 스타일을 기반으로 레이아웃 패턴 밀도를 명시적으로 제어하고 수학적 최적화 접근 방식을 제공하기 위해 밀도 인식 레이아웃 형식을 도입합니다. 따라서 밀도 최적화를 통합한 설계 흐름은 반복 횟수를 줄여 설계 시간을 대폭 단축할 수 있습니다. 65nm CMOS 공정의 OPAMP 레이아웃 설계 사례에서 결과는 제안된 접근 방식이 기존 수동 레이아웃에 비해 48배 이상 속도 향상을 달성하는 동시에 레이아웃 후 시뮬레이션에서 우수한 회로 성능을 보여줍니다.
Chao GENG
The University of Kitakyushu
Bo LIU
Henan University of Science and Technology
Shigetoshi NAKATAKE
The University of Kitakyushu
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부
Chao GENG, Bo LIU, Shigetoshi NAKATAKE, "Density Optimization for Analog Layout Based on Transistor-Array" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 12, pp. 1720-1730, December 2019, doi: 10.1587/transfun.E102.A.1720.
Abstract: In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.1720/_p
부
@ARTICLE{e102-a_12_1720,
author={Chao GENG, Bo LIU, Shigetoshi NAKATAKE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Density Optimization for Analog Layout Based on Transistor-Array},
year={2019},
volume={E102-A},
number={12},
pages={1720-1730},
abstract={In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.},
keywords={},
doi={10.1587/transfun.E102.A.1720},
ISSN={1745-1337},
month={December},}
부
TY - JOUR
TI - Density Optimization for Analog Layout Based on Transistor-Array
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1720
EP - 1730
AU - Chao GENG
AU - Bo LIU
AU - Shigetoshi NAKATAKE
PY - 2019
DO - 10.1587/transfun.E102.A.1720
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2019
AB - In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.
ER -