The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
나노포토닉 소자를 이용한 광회로는 초고속 동작으로 인해 큰 관심을 끌고 있다. 결과적으로, 광회로의 합성 방법 또한 점점 더 많은 관심을 끌고 있습니다. 그러나 광학 회로를 합성하는 기존 방법은 대부분 BDD(이진 결정 다이어그램)와 같은 확립된 데이터 구조의 간단한 매핑에 의존합니다. 단순히 BDD를 광학 회로에 매핑하는 전략은 때때로 크기가 폭발적으로 증가하고 분기 및 광학 장치에서 상당한 전력 손실을 초래합니다. 이러한 문제를 해결하기 위해 본 논문에서는 WDM(wavelength Division Multiplexing)을 활용하여 BDD 기반 광논리회로의 크기를 줄이는 방법을 제안한다. 또한 본 논문에서는 BDD 기반 회로의 분기 수를 줄여 레이저 광원의 전력 소모를 줄이는 방법을 제안합니다. 4비트 병렬 승산기에 사용된 부분 곱 누적 회로를 사용하여 얻은 실험 결과는 면적 및 전력 소비 측면에서 기존 접근 방식에 비해 우리 방법의 상당한 이점을 보여줍니다.
Ryosuke MATSUO
Kyoto University
Jun SHIOMI
Kyoto University
Tohru ISHIHARA
Kyoto University
Hidetoshi ONODERA
Kyoto University
Akihiko SHINYA
NTT Corporation
Masaya NOTOMI
NTT Corporation
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Ryosuke MATSUO, Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA, Akihiko SHINYA, Masaya NOTOMI, "Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 12, pp. 1751-1759, December 2019, doi: 10.1587/transfun.E102.A.1751.
Abstract: Optical circuits using nanophotonic devices attract significant interest due to its ultra-high speed operation. As a consequence, the synthesis methods for the optical circuits also attract increasing attention. However, existing methods for synthesizing optical circuits mostly rely on straight-forward mappings from established data structures such as Binary Decision Diagram (BDD). The strategy of simply mapping a BDD to an optical circuit sometimes results in an explosion of size and involves significant power losses in branches and optical devices. To address these issues, this paper proposes a method for reducing the size of BDD-based optical logic circuits exploiting wavelength division multiplexing (WDM). The paper also proposes a method for reducing the number of branches in a BDD-based circuit, which reduces the power dissipation in laser sources. Experimental results obtained using a partial product accumulation circuit used in a 4-bit parallel multiplier demonstrates significant advantages of our method over existing approaches in terms of area and power consumption.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.1751/_p
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@ARTICLE{e102-a_12_1751,
author={Ryosuke MATSUO, Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA, Akihiko SHINYA, Masaya NOTOMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits},
year={2019},
volume={E102-A},
number={12},
pages={1751-1759},
abstract={Optical circuits using nanophotonic devices attract significant interest due to its ultra-high speed operation. As a consequence, the synthesis methods for the optical circuits also attract increasing attention. However, existing methods for synthesizing optical circuits mostly rely on straight-forward mappings from established data structures such as Binary Decision Diagram (BDD). The strategy of simply mapping a BDD to an optical circuit sometimes results in an explosion of size and involves significant power losses in branches and optical devices. To address these issues, this paper proposes a method for reducing the size of BDD-based optical logic circuits exploiting wavelength division multiplexing (WDM). The paper also proposes a method for reducing the number of branches in a BDD-based circuit, which reduces the power dissipation in laser sources. Experimental results obtained using a partial product accumulation circuit used in a 4-bit parallel multiplier demonstrates significant advantages of our method over existing approaches in terms of area and power consumption.},
keywords={},
doi={10.1587/transfun.E102.A.1751},
ISSN={1745-1337},
month={December},}
부
TY - JOUR
TI - Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1751
EP - 1759
AU - Ryosuke MATSUO
AU - Jun SHIOMI
AU - Tohru ISHIHARA
AU - Hidetoshi ONODERA
AU - Akihiko SHINYA
AU - Masaya NOTOMI
PY - 2019
DO - 10.1587/transfun.E102.A.1751
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2019
AB - Optical circuits using nanophotonic devices attract significant interest due to its ultra-high speed operation. As a consequence, the synthesis methods for the optical circuits also attract increasing attention. However, existing methods for synthesizing optical circuits mostly rely on straight-forward mappings from established data structures such as Binary Decision Diagram (BDD). The strategy of simply mapping a BDD to an optical circuit sometimes results in an explosion of size and involves significant power losses in branches and optical devices. To address these issues, this paper proposes a method for reducing the size of BDD-based optical logic circuits exploiting wavelength division multiplexing (WDM). The paper also proposes a method for reducing the number of branches in a BDD-based circuit, which reduces the power dissipation in laser sources. Experimental results obtained using a partial product accumulation circuit used in a 4-bit parallel multiplier demonstrates significant advantages of our method over existing approaches in terms of area and power consumption.
ER -