The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
MIPI(Mobile Industry Processor Interface) D-PHY 버전 3를 지원하는 FPGA(Field-Programmable Gate Array) 기반 프레임 생성기를 위해 고속 모드 감지기를 포함하는 1.2Gbps/레인 전송 버퍼 칩을 제안한다. LVDS(저전압 차동 신호) 또는 SLVS(확장형 저전압 신호)를 SLVS로 버퍼링하면서 1-3 반복을 수행합니다.
Pil-Ho LEE
Kumoh National Institute of Technology
Young-Chan JANG
Kumoh National Institute of Technology
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부
Pil-Ho LEE, Young-Chan JANG, "A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 6, pp. 783-787, June 2019, doi: 10.1587/transfun.E102.A.783.
Abstract: A 3Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.783/_p
부
@ARTICLE{e102-a_6_783,
author={Pil-Ho LEE, Young-Chan JANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip},
year={2019},
volume={E102-A},
number={6},
pages={783-787},
abstract={A 3Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.},
keywords={},
doi={10.1587/transfun.E102.A.783},
ISSN={1745-1337},
month={June},}
부
TY - JOUR
TI - A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 783
EP - 787
AU - Pil-Ho LEE
AU - Young-Chan JANG
PY - 2019
DO - 10.1587/transfun.E102.A.783
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2019
AB - A 3Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.
ER -