The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
최근 및 미래의 나노미터 기술 VLSI의 경우 정적 및 동적 지연 변동이 심각한 문제가 됩니다. 대부분의 경우 설정 제약뿐 아니라 홀드 제약도 지연 변화에 따라 올바른 신호를 래칭하는 데 매우 중요합니다. 본 논문에서는 데이터 경로 회로의 홀드 제약을 다루고 지연 변화를 고려한 상위 레벨 합성의 레지스터 할당에 대해 논의합니다. 지연 변화에 따른 홀드 제약을 보장하기 위한 우리의 접근 방식은 레지스터 간 최소 경로 지연을 확대하는 것인데, 이를 본 논문에서는 최소 경로 지연 보상(MDC)이라고 합니다. MDC는 주로 기능 단위(FU)의 중요하지 않은 경로에 지연 요소를 삽입하여 수행할 수 있습니다. 우리의 기여 중 하나는 최소 경로 지연 보상 FU 수의 최소화가 일반적으로 NP-hard이며 FU 수가 상수인 경우 클래스 P에 있음을 보여주는 것입니다. 후자에 대한 다항식 시간 알고리즘도 이 논문에 나와 있습니다. 또한 정수 선형 계획법(ILP) 공식도 제시됩니다. 제안된 방법은 (1) 부분적으로 MDC 기술과 부분적으로 SRV 기반 레지스터 할당에 의해 보장되는 지연 변화에 대한 견고성과 (2) 가능한 최소 MDC 및 레지스터 수를 갖는 데이터 경로를 생성합니다.
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부
Keisuke INOUE, Mineo KANEKO, Tsuyoshi IWAGAKI, "Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 4, pp. 1096-1105, April 2009, doi: 10.1587/transfun.E92.A.1096.
Abstract: For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1096/_p
부
@ARTICLE{e92-a_4_1096,
author={Keisuke INOUE, Mineo KANEKO, Tsuyoshi IWAGAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths},
year={2009},
volume={E92-A},
number={4},
pages={1096-1105},
abstract={For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.},
keywords={},
doi={10.1587/transfun.E92.A.1096},
ISSN={1745-1337},
month={April},}
부
TY - JOUR
TI - Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1096
EP - 1105
AU - Keisuke INOUE
AU - Mineo KANEKO
AU - Tsuyoshi IWAGAKI
PY - 2009
DO - 10.1587/transfun.E92.A.1096
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2009
AB - For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.
ER -