The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
단락 및 개방은 초대형 집적 회로에서 발생할 가능성이 가장 높은 두 가지 주요 결함입니다. 최신 집적 회로 장치에서는 이러한 결함을 게이트 수준뿐만 아니라 트랜지스터 수준에서도 고려해야 합니다. 본 논문에서는 트랜지스터 단락(tr-shorts)과 트랜지스터 개방(tr-opens)을 모두 대상으로 하는 테스트 벡터를 생성하는 방법을 제안합니다. tr-open을 감지하려면 두 개의 연속적인 테스트 벡터를 적용해야 하므로 LOC(Launch on Capture) 테스트 적용 메커니즘을 가정합니다. 이를 통해 지연 유형 결함을 감지할 수 있습니다. 또한 제안된 방법은 기존의 정체된 테스트 생성 도구를 사용하므로 설계 및 개발 흐름을 변경할 필요가 없으며 새로운 도구를 개발할 필요도 없습니다. 벤치마크 회로에 대한 실험 결과는 테스트 세트 크기가 여전히 적당한 수준인 동안 100% 오류 효율성을 제공함으로써 제안된 방법의 효율성을 보여줍니다.
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Yoshinobu HIGAMI, Kewal K. SALUJA, Hiroshi TAKAHASHI, Shin-ya KOBAYASHI, Yuzo TAKAMATSU, "Addressing Defect Coverage through Generating Test Vectors for Transistor Defects" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3128-3135, December 2009, doi: 10.1587/transfun.E92.A.3128.
Abstract: Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3128/_p
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@ARTICLE{e92-a_12_3128,
author={Yoshinobu HIGAMI, Kewal K. SALUJA, Hiroshi TAKAHASHI, Shin-ya KOBAYASHI, Yuzo TAKAMATSU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Addressing Defect Coverage through Generating Test Vectors for Transistor Defects},
year={2009},
volume={E92-A},
number={12},
pages={3128-3135},
abstract={Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.},
keywords={},
doi={10.1587/transfun.E92.A.3128},
ISSN={1745-1337},
month={December},}
부
TY - JOUR
TI - Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3128
EP - 3135
AU - Yoshinobu HIGAMI
AU - Kewal K. SALUJA
AU - Hiroshi TAKAHASHI
AU - Shin-ya KOBAYASHI
AU - Yuzo TAKAMATSU
PY - 2009
DO - 10.1587/transfun.E92.A.3128
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.
ER -