The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
하위 임계값 MOSFET 회로로 구성된 임계값 논리 게이트 장치가 제안됩니다. 게이트 장치는 전류 모드 덧셈 및 뺄셈 기술을 사용하여 임계값 논리 연산을 수행합니다. 임계 논리를 기반으로 하는 가산기 및 형태학적 연산 셀과 같은 샘플 디지털 하위 시스템은 게이트 장치를 사용하여 설계되고 해당 동작은 컴퓨터 시뮬레이션을 통해 확인됩니다. 이 장치는 구조가 간단하고 전력 소모가 낮기 때문에 셀룰러 오토마톤, 신경망 LSI 등 셀 기반 병렬 처리 LSI를 구축하는 데 적합합니다.
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Taichi OGAWA, Tetsuya HIROSE, Tetsuya ASAI, Yoshihito AMEMIYA, "Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 2, pp. 436-442, February 2009, doi: 10.1587/transfun.E92.A.436.
Abstract: A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.436/_p
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@ARTICLE{e92-a_2_436,
author={Taichi OGAWA, Tetsuya HIROSE, Tetsuya ASAI, Yoshihito AMEMIYA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits},
year={2009},
volume={E92-A},
number={2},
pages={436-442},
abstract={A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.},
keywords={},
doi={10.1587/transfun.E92.A.436},
ISSN={1745-1337},
month={February},}
부
TY - JOUR
TI - Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 436
EP - 442
AU - Taichi OGAWA
AU - Tetsuya HIROSE
AU - Tetsuya ASAI
AU - Yoshihito AMEMIYA
PY - 2009
DO - 10.1587/transfun.E92.A.436
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2009
AB - A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.
ER -