The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
대칭 제약은 아날로그 IC 설계에서 주어진 셀이 대칭적으로 배치되어야 한다는 제약입니다. 우리는 O-트리를 사용하여 배치를 표현하고 제약 조건을 만족하는 최소 배치 중 하나를 얻을 수 있는 디코딩 알고리즘을 제안합니다. 디코딩 알고리즘은 선형 프로그래밍을 사용하므로 시간이 너무 많이 걸립니다. 따라서 우리는 주어진 대칭성과 O-트리 제약 조건을 모두 만족하는 배치가 존재하지 않는지 여부를 인식하고 선형 프로그래밍을 적용하기 전에 이 방법을 사용하는 그래프 기반 방법을 제안합니다. 제안된 방법의 효율성은 컴퓨터 실험을 통해 나타났다.
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Natsumi HIRAKAWA, Kunihiro FUJIYOSHI, "Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 2, pp. 467-474, February 2009, doi: 10.1587/transfun.E92.A.467.
Abstract: Symmetry constrains are the constraints that the given cells should be placed symmetrically in design of analog ICs. We use O-tree to represent placements and propose a decoding algorithm which can obtain one of the minimum placements satisfying the constraints. The decoding algorithm uses linear programming, which is too much time consuming. Therefore we propose a graph based method to recognize if there exists no placement satisfying both the given symmetry and O-tree constraints, and use the method before application of linear programming. The effectiveness of the proposed method was shown by computational experiments.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.467/_p
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@ARTICLE{e92-a_2_467,
author={Natsumi HIRAKAWA, Kunihiro FUJIYOSHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation},
year={2009},
volume={E92-A},
number={2},
pages={467-474},
abstract={Symmetry constrains are the constraints that the given cells should be placed symmetrically in design of analog ICs. We use O-tree to represent placements and propose a decoding algorithm which can obtain one of the minimum placements satisfying the constraints. The decoding algorithm uses linear programming, which is too much time consuming. Therefore we propose a graph based method to recognize if there exists no placement satisfying both the given symmetry and O-tree constraints, and use the method before application of linear programming. The effectiveness of the proposed method was shown by computational experiments.},
keywords={},
doi={10.1587/transfun.E92.A.467},
ISSN={1745-1337},
month={February},}
부
TY - JOUR
TI - Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 467
EP - 474
AU - Natsumi HIRAKAWA
AU - Kunihiro FUJIYOSHI
PY - 2009
DO - 10.1587/transfun.E92.A.467
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2009
AB - Symmetry constrains are the constraints that the given cells should be placed symmetrically in design of analog ICs. We use O-tree to represent placements and propose a decoding algorithm which can obtain one of the minimum placements satisfying the constraints. The decoding algorithm uses linear programming, which is too much time consuming. Therefore we propose a graph based method to recognize if there exists no placement satisfying both the given symmetry and O-tree constraints, and use the method before application of linear programming. The effectiveness of the proposed method was shown by computational experiments.
ER -