The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
딥 서브미크론 시대에는 와이어 지연이 더 이상 무시할 수 없으며 시스템 성능의 지배적인 요소가 되고 있습니다. 증가하는 와이어 지연에 대처하기 위해 온칩 다중 사이클 통신을 활성화함으로써 분산 레지스터 아키텍처에 대한 여러 가지 최첨단 아키텍처 합성 흐름이 제안되었습니다. 이 기사에서는 일반 분산 레지스터 아키텍처를 대상으로 하는 새로운 성능 중심 임계성 인식 합성 프레임워크 CriAS를 제시합니다. 높은 시스템 성능을 달성하기 위해 CriAS는 성능이 중요한 글로벌 데이터 전송 횟수를 최소화하기 위한 계층적 바인딩 후 배치 기능을 제공합니다. 핵심 아이디어는 자세한 물리적 배치 정보가 제공되기 전 초기 바인딩 단계에서 시간 중요성을 주요 관심사로 삼고, 이후 배치 단계에서 밀접하게 관련된 중요 구성 요소의 위치를 보존하는 것입니다. 실험 결과는 CriAS가 이전 기술에 비해 런타임 오버헤드 없이 평균 14.26%의 전체 성능 향상을 달성할 수 있음을 보여줍니다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Chia-I CHEN, Juinn-Dar HUANG, "A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 7, pp. 1300-1308, July 2010, doi: 10.1587/transfun.E93.A.1300.
Abstract: In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1300/_p
부
@ARTICLE{e93-a_7_1300,
author={Chia-I CHEN, Juinn-Dar HUANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication},
year={2010},
volume={E93-A},
number={7},
pages={1300-1308},
abstract={In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.},
keywords={},
doi={10.1587/transfun.E93.A.1300},
ISSN={1745-1337},
month={July},}
부
TY - JOUR
TI - A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1300
EP - 1308
AU - Chia-I CHEN
AU - Juinn-Dar HUANG
PY - 2010
DO - 10.1587/transfun.E93.A.1300
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2010
AB - In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.
ER -