The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 비용 효율적인 DVB-S2용 LDPC 디코더를 제시한다. Normalized Min-Sum 알고리즘과 TDMP(turbo-decoding message-passing) 알고리즘을 기반으로 하드웨어 재사용이 가능하도록 듀얼 라인 스캔 스케줄링을 제안합니다. 또한 DVB-S2 LDPC 코드에서 정의하는 패리티 검사 행렬의 특성으로 인해 발생하는 주소 충돌 문제에 대한 해결책을 제시한다. SMIC 0.13 µm 표준 CMOS 프로세스를 기반으로 하는 LDPC 디코더의 면적은 12.51 mm입니다.2. 최대 반복 횟수 135회에서 30Mbps의 처리량 요구 사항을 충족하는 데 필요한 작동 주파수는 105MHz입니다. 최근 발표된 DVB-S2 LDPC 디코더와 비교하여 제안된 디코더는 면적 비용을 34% 절감합니다.
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부
Yan YING, Dan BAO, Zhiyi YU, Xiaoyang ZENG, Yun CHEN, "A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 8, pp. 1415-1424, August 2010, doi: 10.1587/transfun.E93.A.1415.
Abstract: In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13 µm standard CMOS process, the LDPC decoder has an area of 12.51 mm2. The required operating frequency to meet the throughput requirement of 135 Mbps with maximum iteration number of 30 is 105 MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1415/_p
부
@ARTICLE{e93-a_8_1415,
author={Yan YING, Dan BAO, Zhiyi YU, Xiaoyang ZENG, Yun CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue},
year={2010},
volume={E93-A},
number={8},
pages={1415-1424},
abstract={In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13 µm standard CMOS process, the LDPC decoder has an area of 12.51 mm2. The required operating frequency to meet the throughput requirement of 135 Mbps with maximum iteration number of 30 is 105 MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.},
keywords={},
doi={10.1587/transfun.E93.A.1415},
ISSN={1745-1337},
month={August},}
부
TY - JOUR
TI - A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1415
EP - 1424
AU - Yan YING
AU - Dan BAO
AU - Zhiyi YU
AU - Xiaoyang ZENG
AU - Yun CHEN
PY - 2010
DO - 10.1587/transfun.E93.A.1415
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2010
AB - In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13 µm standard CMOS process, the LDPC decoder has an area of 12.51 mm2. The required operating frequency to meet the throughput requirement of 135 Mbps with maximum iteration number of 30 is 105 MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.
ER -