The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
배전 네트워크의 상태 의존적 커패시턴스를 위한 빠른 계산 도구가 제안되었습니다. 제안된 방법은 기존 SPICE 기반 커패시턴스 계산보다 5배 이상 빠른 선형 시간 복잡도를 달성합니다. 기존 방법으로는 분석할 수 없었던 대규모 회로를 분석하여 정전용량 변화를 보다 포괄적으로 탐색할 수 있습니다. 제안한 방법으로 얻은 정전용량은 SPICE 기반 방법과 완전히 일치하며(최대 XNUMX자리), 다양한 회로에 대한 수치 실험을 통해 시간 선형성을 확인하였다. 최대 및 최소 커패시턴스는 평균 및 분산 추정을 사용하여 계산됩니다. 계산 시간 역시 선형 시간 복잡도입니다. 제안된 도구는 LSI의 정확한 매크로 모델 구축을 용이하게 합니다.
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부
Shiho HAGIWARA, Koh YAMANAGA, Ryo TAKAHASHI, Kazuya MASU, Takashi SATO, "Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2409-2416, December 2010, doi: 10.1587/transfun.E93.A.2409.
Abstract: A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2409/_p
부
@ARTICLE{e93-a_12_2409,
author={Shiho HAGIWARA, Koh YAMANAGA, Ryo TAKAHASHI, Kazuya MASU, Takashi SATO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence},
year={2010},
volume={E93-A},
number={12},
pages={2409-2416},
abstract={A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI.},
keywords={},
doi={10.1587/transfun.E93.A.2409},
ISSN={1745-1337},
month={December},}
부
TY - JOUR
TI - Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2409
EP - 2416
AU - Shiho HAGIWARA
AU - Koh YAMANAGA
AU - Ryo TAKAHASHI
AU - Kazuya MASU
AU - Takashi SATO
PY - 2010
DO - 10.1587/transfun.E93.A.2409
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI.
ER -