The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
일반적인 SoC(System-on-Chip) 설계에서는 많은 수의 트랜지스터의 총 스위칭으로 인해 활성 클록 에지 근처에서 거대한 피크 전류가 발생하는 경우가 많습니다. SoC 설계에서 순수 상승(하강) 트리거링 에지 중 하나가 아닌 혼합 상승 및 하강 트리거링 에지의 클록 방식을 사용할 수 있는 경우 총 스위칭 트랜지스터의 수를 줄일 수 있습니다. 본 논문에서는 주어진 IP 기반 SoC/NoC(Network-on-NoC)의 각 IP 코어의 각 클럭에 상승 트리거링 에지 또는 하강 트리거링 에지를 할당할 수 있는 클럭 트리거링 에지 할당 기법과 알고리즘을 제안한다. 칩) 디자인. 알고리즘의 목표는 설계의 피크 전류를 줄이는 것입니다. 제안한 기법은 소프트웨어 시스템으로 구현되었다. 시스템은 LP 기술을 사용하여 몇 초 내에 최적 또는 차선 솔루션을 찾을 수 있습니다. 시스템은 또한 ILP 기법을 사용하여 최적의 솔루션을 찾을 수 있지만 ILP 기법은 복잡한 설계를 해결하는 데 사용하기에 적합하지 않습니다. 실험 결과에 따르면 당사의 알고리즘은 피크 전류를 최대 56.3%까지 줄일 수 있습니다.
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Tsung-Yi WU, Tzi-Wei KAO, How-Rern LIN, "Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2581-2589, December 2010, doi: 10.1587/transfun.E93.A.2581.
Abstract: In a typical SoC (System-on-Chip) design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core of a given IP-based SoC/NoC (Network-on-Chip) design. The goal of the algorithms is to reduce the peak current of the design. Our proposed technique has been implemented as a software system. The system can use an LP technique to find an optimal or suboptimal solution within several seconds. The system also can use an ILP technique to find an optimal solution, but the ILP technique is not suitable to be used to solve a complex design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2581/_p
부
@ARTICLE{e93-a_12_2581,
author={Tsung-Yi WU, Tzi-Wei KAO, How-Rern LIN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs},
year={2010},
volume={E93-A},
number={12},
pages={2581-2589},
abstract={In a typical SoC (System-on-Chip) design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core of a given IP-based SoC/NoC (Network-on-Chip) design. The goal of the algorithms is to reduce the peak current of the design. Our proposed technique has been implemented as a software system. The system can use an LP technique to find an optimal or suboptimal solution within several seconds. The system also can use an ILP technique to find an optimal solution, but the ILP technique is not suitable to be used to solve a complex design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.},
keywords={},
doi={10.1587/transfun.E93.A.2581},
ISSN={1745-1337},
month={December},}
부
TY - JOUR
TI - Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2581
EP - 2589
AU - Tsung-Yi WU
AU - Tzi-Wei KAO
AU - How-Rern LIN
PY - 2010
DO - 10.1587/transfun.E93.A.2581
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - In a typical SoC (System-on-Chip) design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core of a given IP-based SoC/NoC (Network-on-Chip) design. The goal of the algorithms is to reduce the peak current of the design. Our proposed technique has been implemented as a software system. The system can use an LP technique to find an optimal or suboptimal solution within several seconds. The system also can use an ILP technique to find an optimal solution, but the ILP technique is not suitable to be used to solve a complex design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.
ER -