The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
최근 첨단 기술로 인해 디지털 회로가 소형화되고 단일 칩에 집적할 수 있는 디지털 기능 블록의 수가 급증하고 있습니다. 반면, 아날로그 회로의 크기 감소는 충분하지 않았습니다. 이는 아날로그 회로 면적이 상대적으로 크다는 의미이며, 아날로그 회로 면적을 줄이는 것이 저가의 무선 수신기를 만드는데 효과적일 수 있다는 뜻이다. 본 논문에서는 작은 아날로그 면적을 차지하는 새로운 무선 수신기 아키텍처를 제안하고, 핵심 아날로그 블록의 측정 결과를 기술한다. 아날로그 영역을 줄이기 위해 밸런스드 3상 아날로그 시스템을 채택하고 아날로그 베이스밴드 필터와 VGA의 기능을 디지털 영역으로 옮겼습니다. 테스트 칩은 3상 다운컨버터와 3상 ADC로 구성됩니다. 칩에는 아날로그 베이스밴드 필터가 없으며 아날로그 필터는 디지털 필터로 대체되는 것으로 가정됩니다. 다운컨버터와 ADC는 0.28mm를 차지합니다.2. 측정된 결과는 작은 칩 면적으로도 IMT-2000의 요구 사항을 충족할 가능성을 보여줍니다.
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Takafumi YAMAJI, Takeshi UENO, Tetsuro ITAKURA, "A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 2, pp. 367-374, February 2010, doi: 10.1587/transfun.E93.A.367.
Abstract: Recent advanced technology makes digital circuits small and the number of digital functional blocks that can be integrated on a single chip is increasing rapidly. On the other hand, reduction in the size of analog circuits has been insufficient. This means that the analog circuit area is relatively large, and reducing analog circuit area can be effective to make a low cost radio receiver. In this paper, a new wireless receiver architecture that occupies small analog area is proposed, and measured results of the core analog blocks are described. To reduce the analog area, a balanced 3-phase analog system is adopted and the functions of analog baseband filters and VGAs are moved to the digital domain. The test chip consists of a 3-phase downconverter and a 3-phase ADC. There is no analog baseband filter on the chip and the analog filter is assumed to be replaced with a digital filter. The downconverter and ADC occupy 0.28 mm2. The measured results show the possibility that the requirements for IMT-2000 are fulfilled even with a small chip area.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.367/_p
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@ARTICLE{e93-a_2_367,
author={Takafumi YAMAJI, Takeshi UENO, Tetsuro ITAKURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System},
year={2010},
volume={E93-A},
number={2},
pages={367-374},
abstract={Recent advanced technology makes digital circuits small and the number of digital functional blocks that can be integrated on a single chip is increasing rapidly. On the other hand, reduction in the size of analog circuits has been insufficient. This means that the analog circuit area is relatively large, and reducing analog circuit area can be effective to make a low cost radio receiver. In this paper, a new wireless receiver architecture that occupies small analog area is proposed, and measured results of the core analog blocks are described. To reduce the analog area, a balanced 3-phase analog system is adopted and the functions of analog baseband filters and VGAs are moved to the digital domain. The test chip consists of a 3-phase downconverter and a 3-phase ADC. There is no analog baseband filter on the chip and the analog filter is assumed to be replaced with a digital filter. The downconverter and ADC occupy 0.28 mm2. The measured results show the possibility that the requirements for IMT-2000 are fulfilled even with a small chip area.},
keywords={},
doi={10.1587/transfun.E93.A.367},
ISSN={1745-1337},
month={February},}
부
TY - JOUR
TI - A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 367
EP - 374
AU - Takafumi YAMAJI
AU - Takeshi UENO
AU - Tetsuro ITAKURA
PY - 2010
DO - 10.1587/transfun.E93.A.367
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2010
AB - Recent advanced technology makes digital circuits small and the number of digital functional blocks that can be integrated on a single chip is increasing rapidly. On the other hand, reduction in the size of analog circuits has been insufficient. This means that the analog circuit area is relatively large, and reducing analog circuit area can be effective to make a low cost radio receiver. In this paper, a new wireless receiver architecture that occupies small analog area is proposed, and measured results of the core analog blocks are described. To reduce the analog area, a balanced 3-phase analog system is adopted and the functions of analog baseband filters and VGAs are moved to the digital domain. The test chip consists of a 3-phase downconverter and a 3-phase ADC. There is no analog baseband filter on the chip and the analog filter is assumed to be replaced with a digital filter. The downconverter and ADC occupy 0.28 mm2. The measured results show the possibility that the requirements for IMT-2000 are fulfilled even with a small chip area.
ER -