The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 높은 효율과 작은 출력 리플 전압을 달성하기 위해 세 가지 동작 모드를 갖춘 승압/강압 DC-DC 컨버터를 제시합니다. 원활한 전환을 위해 벅 모드와 부스트 모드 사이에 삽입되는 정시간 벅-부스트 모드가 제안되었습니다. 제안된 모드에서는 입력 전압이 출력 전압에 가까워질 때 출력 리플 전압이 크게 감소합니다. 또한, 새로운 제어 방식은 컨버터를 벅 또는 부스트 컨버터처럼 작동시켜 평균 인덕터 전류와 스위칭 손실을 줄여 전도 손실을 최소화합니다. 승압/강압 DC-DC 컨버터의 소신호 모델도 보상 네트워크 설계를 안내하기 위해 파생되었습니다. 승압/강압 컨버터는 0.5 µm CMOS n-well 프로세스로 설계되었으며 최대 전력 효율 2.5%로 5.5V ~ 96V 범위의 입력 전압 내에서 출력 전압을 조절할 수 있습니다. 시뮬레이션 결과는 제안된 컨버터가 천이 모드에서 28mV의 출력 리플 전압을 나타내는 것을 보여준다.
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Yanzhao MA, Hongyi WANG, Guican CHEN, "Design and Modeling of a High Efficiency Step-Up/Step-Down DC-DC Converter with Smooth Transition" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 2, pp. 646-652, February 2011, doi: 10.1587/transfun.E94.A.646.
Abstract: This paper presents a step-up/step-down DC-DC converter with three operation modes to achieve high efficiency and small output ripple voltage. A constant time buck-boost mode, which is inserted between buck mode and boost mode, is proposed to achieve smooth transition. With the proposed mode, the output ripple voltage is significantly reduced when the input voltage is approximate to the output voltage. Besides, the novel control scheme minimizes the conduction loss by reducing the average inductor current and the switching loss by making the converter operate like a buck or boost converter. The small signal model of the step-up/step-down DC-DC converter is also derived to guide the compensation network design. The step-up/step-down converter is designed with a 0.5 µm CMOS n-well process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V with a maximum power efficiency of 96%. The simulation results show that the proposed converter exhibits an output ripple voltage of 28 mV in the transition mode.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.646/_p
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@ARTICLE{e94-a_2_646,
author={Yanzhao MA, Hongyi WANG, Guican CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design and Modeling of a High Efficiency Step-Up/Step-Down DC-DC Converter with Smooth Transition},
year={2011},
volume={E94-A},
number={2},
pages={646-652},
abstract={This paper presents a step-up/step-down DC-DC converter with three operation modes to achieve high efficiency and small output ripple voltage. A constant time buck-boost mode, which is inserted between buck mode and boost mode, is proposed to achieve smooth transition. With the proposed mode, the output ripple voltage is significantly reduced when the input voltage is approximate to the output voltage. Besides, the novel control scheme minimizes the conduction loss by reducing the average inductor current and the switching loss by making the converter operate like a buck or boost converter. The small signal model of the step-up/step-down DC-DC converter is also derived to guide the compensation network design. The step-up/step-down converter is designed with a 0.5 µm CMOS n-well process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V with a maximum power efficiency of 96%. The simulation results show that the proposed converter exhibits an output ripple voltage of 28 mV in the transition mode.},
keywords={},
doi={10.1587/transfun.E94.A.646},
ISSN={1745-1337},
month={February},}
부
TY - JOUR
TI - Design and Modeling of a High Efficiency Step-Up/Step-Down DC-DC Converter with Smooth Transition
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 646
EP - 652
AU - Yanzhao MA
AU - Hongyi WANG
AU - Guican CHEN
PY - 2011
DO - 10.1587/transfun.E94.A.646
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2011
AB - This paper presents a step-up/step-down DC-DC converter with three operation modes to achieve high efficiency and small output ripple voltage. A constant time buck-boost mode, which is inserted between buck mode and boost mode, is proposed to achieve smooth transition. With the proposed mode, the output ripple voltage is significantly reduced when the input voltage is approximate to the output voltage. Besides, the novel control scheme minimizes the conduction loss by reducing the average inductor current and the switching loss by making the converter operate like a buck or boost converter. The small signal model of the step-up/step-down DC-DC converter is also derived to guide the compensation network design. The step-up/step-down converter is designed with a 0.5 µm CMOS n-well process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V with a maximum power efficiency of 96%. The simulation results show that the proposed converter exhibits an output ripple voltage of 28 mV in the transition mode.
ER -