The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
IEEE 1500 표준 래퍼에서는 제어 가능성과 관찰 가능성을 위해 입력 및 출력이 칩의 기본 입력 및 출력에 직접 인터페이스되어야 합니다. 이는 일반적으로 래퍼와 기본 입력 및 출력 사이에 전용 TAM(테스트 액세스 메커니즘)을 제공하여 달성됩니다. 그러나 전용 TAM 대신 내장된 NoC(Network-on-Chip) 상호 연결을 재사용하는 경우 NoC의 패킷 기반 전송 메커니즘 및 기타 기능 요구 사항으로 인해 표준 래퍼를 그대로 사용할 수 없습니다. 본 논문에서는 1500 래퍼의 이러한 한계를 극복하는 두 가지 NoC 호환 래퍼에 대해 설명합니다. 래퍼(유형 1 및 유형 2)는 서로를 보완하여 NoC 대역폭 활용을 최적화하는 동시에 영역 오버헤드를 최소화합니다. 유형 2 래퍼는 더 넓은 영역 오버헤드를 사용하여 대역폭 효율성을 높이는 반면, 유형 1은 복잡하고 비용이 많이 드는 래퍼가 필요하지 않은 일부 특수 구성을 활용합니다. 두 개의 래퍼 최적화 알고리즘이 채널 대역폭 및 테스트 시간 제약 하에서 두 래퍼 디자인 모두에 적용되므로 기존의 전용 TAM 접근 방식에 비해 테스트 적용 시간이 거의 또는 전혀 증가하지 않습니다.
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Fawnizu Azmadi HUSSIN, Tomokazu YONEDA, Hideo FUJIWARA, "NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 7, pp. 2008-2017, July 2008, doi: 10.1093/ietisy/e91-d.7.2008.
Abstract: The IEEE 1500 standard wrapper requires that its inputs and outputs be interfaced directly to the chip's primary inputs and outputs for controllability and observability. This is typically achieved by providing a dedicated Test Access Mechanism (TAM) between the wrapper and the primary inputs and outputs. However, when reusing the embedded Network-on-Chip (NoC) interconnect instead of the dedicated TAM, the standard wrapper cannot be used as is because of the packet-based transfer mechanism and other functional requirements by the NoC. In this paper, we describe two NoC-compatible wrappers, which overcome these limitations of the 1500 wrapper. The wrappers (Type 1 and Type 2) complement each other to optimize NoC bandwidth utilization while minimizing the area overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel-bandwidth and test-time constraints, resulting in very little or no increase in the test application time compared to conventional dedicated TAM approaches.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.7.2008/_p
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@ARTICLE{e91-d_7_2008,
author={Fawnizu Azmadi HUSSIN, Tomokazu YONEDA, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints},
year={2008},
volume={E91-D},
number={7},
pages={2008-2017},
abstract={The IEEE 1500 standard wrapper requires that its inputs and outputs be interfaced directly to the chip's primary inputs and outputs for controllability and observability. This is typically achieved by providing a dedicated Test Access Mechanism (TAM) between the wrapper and the primary inputs and outputs. However, when reusing the embedded Network-on-Chip (NoC) interconnect instead of the dedicated TAM, the standard wrapper cannot be used as is because of the packet-based transfer mechanism and other functional requirements by the NoC. In this paper, we describe two NoC-compatible wrappers, which overcome these limitations of the 1500 wrapper. The wrappers (Type 1 and Type 2) complement each other to optimize NoC bandwidth utilization while minimizing the area overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel-bandwidth and test-time constraints, resulting in very little or no increase in the test application time compared to conventional dedicated TAM approaches.},
keywords={},
doi={10.1093/ietisy/e91-d.7.2008},
ISSN={1745-1361},
month={July},}
부
TY - JOUR
TI - NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
T2 - IEICE TRANSACTIONS on Information
SP - 2008
EP - 2017
AU - Fawnizu Azmadi HUSSIN
AU - Tomokazu YONEDA
AU - Hideo FUJIWARA
PY - 2008
DO - 10.1093/ietisy/e91-d.7.2008
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2008
AB - The IEEE 1500 standard wrapper requires that its inputs and outputs be interfaced directly to the chip's primary inputs and outputs for controllability and observability. This is typically achieved by providing a dedicated Test Access Mechanism (TAM) between the wrapper and the primary inputs and outputs. However, when reusing the embedded Network-on-Chip (NoC) interconnect instead of the dedicated TAM, the standard wrapper cannot be used as is because of the packet-based transfer mechanism and other functional requirements by the NoC. In this paper, we describe two NoC-compatible wrappers, which overcome these limitations of the 1500 wrapper. The wrappers (Type 1 and Type 2) complement each other to optimize NoC bandwidth utilization while minimizing the area overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel-bandwidth and test-time constraints, resulting in very little or no increase in the test application time compared to conventional dedicated TAM approaches.
ER -