The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
인트라 예측 유닛은 H.264 코덱의 필수 부분입니다. 인접 블록의 픽셀 값(휘도 및 색차)을 예측하여 인코딩할 데이터의 양을 줄여주기 때문입니다. 고해상도 비디오 데이터의 실시간 인코딩 및 디코딩에는 인트라 예측 장치에 대한 전용 하드웨어 구현이 필요합니다. 비용 효율적인 인트라 예측 유닛을 개발하기 위해 본 논문에서는 인트라 예측 유닛의 핵심 부분인 인트라 예측 생성기의 새로운 아키텍처를 제안합니다. 제안된 인트라 예측 생성기는 Huang의 연구[3]와 비교하여 인트라 예측 장치가 거의 동일한 게이트 수로 상당한 클록 사이클 감소를 달성할 수 있도록 합니다.
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부
Sanghoon KWAK, Jinwook KIM, Dongsoo HAR, "A Novel Hardware Architecture of Intra-Predictor Generator for H.264/AVC Codec" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 7, pp. 2083-2086, July 2008, doi: 10.1093/ietisy/e91-d.7.2083.
Abstract: The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work [3].
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.7.2083/_p
부
@ARTICLE{e91-d_7_2083,
author={Sanghoon KWAK, Jinwook KIM, Dongsoo HAR, },
journal={IEICE TRANSACTIONS on Information},
title={A Novel Hardware Architecture of Intra-Predictor Generator for H.264/AVC Codec},
year={2008},
volume={E91-D},
number={7},
pages={2083-2086},
abstract={The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work [3].},
keywords={},
doi={10.1093/ietisy/e91-d.7.2083},
ISSN={1745-1361},
month={July},}
부
TY - JOUR
TI - A Novel Hardware Architecture of Intra-Predictor Generator for H.264/AVC Codec
T2 - IEICE TRANSACTIONS on Information
SP - 2083
EP - 2086
AU - Sanghoon KWAK
AU - Jinwook KIM
AU - Dongsoo HAR
PY - 2008
DO - 10.1093/ietisy/e91-d.7.2083
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2008
AB - The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work [3].
ER -