The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
VLSI 기술이 발전함에 따라 웨이퍼 스케일 통합을 사용하여 병렬 컴퓨터 시스템의 전체 또는 상당 부분을 구현하려는 관심이 커지고 있습니다. 이 사례의 가장 큰 문제는 이러한 상황에 대처할 전략이 없을 경우 시스템의 수율 및/또는 신뢰성이 급격히 낮아질 가능성이 있다는 것입니다. 결함이 있는 물리적 시스템을 결함이 없는 대상 논리 시스템으로 재구성하는 다양한 전략이 문헌 [1]-[5]에 설명되어 있습니다. 본 논문에서는 하드웨어와 소프트웨어를 사용하여 결함이 있는 PE가 있는 1 1/2 트랙-스위치 메시 어레이를 재구성할 수 있는 효율적인 근사 방법을 제안합니다. 각 PE에 추가된 논리 회로와 이를 연결하는 네트워크는 결함이 있는 PE를 보상하는 예비 PE를 결정하는 데 사용됩니다. 각 회로의 하드웨어 복잡성은 각 추가 회로의 크기가 어레이 크기와 무관하고 일정한 PE의 복잡성보다 훨씬 적습니다. 전용 하드웨어 방식을 사용함으로써 호스트 컴퓨터를 사용하지 않고 내장된 자체 재구성 시스템을 실현할 수 있으며 어레이 재구성 시간이 매우 단축됩니다. 방법 성능의 시뮬레이션 결과는 우리 알고리즘의 재구성 효율성이 exaustive 및 Shigei의 알고리즘[6]보다 약간 낮지만 신경 알고리즘[7]보다는 훨씬 우수하다는 것을 보여줍니다. 또한 하드웨어 및 소프트웨어에 의한 재구성의 시간 복잡도를 비교하고, 다른 방법 중에서 각 PE에 추가된 논리 회로의 게이트 수 측면에서 하드웨어 복잡도를 비교합니다.
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Tadayoshi HORITA, Itsuo TAKANAMI, "An Efficient Method for Reconfiguring the 1 1/2 Track-Switch Mesh Array" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 12, pp. 1545-1553, December 1999, doi: .
Abstract: As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer scale integration is growing. The major problem for the case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations. Various strategies to restructure the faulty physical system into the fault-free target logical system are described in the literature [1]-[5]. In this paper, we propose an efficient approximate method which can reconstruct the 1 1/2 track-switch mesh arrays with faulty PEs using hardware as well as software. A logical circuit added to each PE and a network connecting the circuits are used to decide spare PEs which compensate for faulty PEs. The hardware compexity of each circuit is much less than that of a PE where the size of each additional circuit is independent of array sizes and constant. By using the exclusive hardware scheme, a built-in self-reconfigurable system without using a host computer is realizable and the time for reconfiguring arrays becomes very short. The simulation result of the performance of the method shows that the reconstructing efficiency of our algorithm is a little less than those of the exaustive and Shigei's ones [6] and [7], but much better than that of the neural one [3]. We also compare the time complexities of reconstructions by hardware as well as software, and the hardware complexity in terms of the number of gates in the logical circuit added to each PE among the other methods.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_12_1545/_p
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@ARTICLE{e82-d_12_1545,
author={Tadayoshi HORITA, Itsuo TAKANAMI, },
journal={IEICE TRANSACTIONS on Information},
title={An Efficient Method for Reconfiguring the 1 1/2 Track-Switch Mesh Array},
year={1999},
volume={E82-D},
number={12},
pages={1545-1553},
abstract={As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer scale integration is growing. The major problem for the case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations. Various strategies to restructure the faulty physical system into the fault-free target logical system are described in the literature [1]-[5]. In this paper, we propose an efficient approximate method which can reconstruct the 1 1/2 track-switch mesh arrays with faulty PEs using hardware as well as software. A logical circuit added to each PE and a network connecting the circuits are used to decide spare PEs which compensate for faulty PEs. The hardware compexity of each circuit is much less than that of a PE where the size of each additional circuit is independent of array sizes and constant. By using the exclusive hardware scheme, a built-in self-reconfigurable system without using a host computer is realizable and the time for reconfiguring arrays becomes very short. The simulation result of the performance of the method shows that the reconstructing efficiency of our algorithm is a little less than those of the exaustive and Shigei's ones [6] and [7], but much better than that of the neural one [3]. We also compare the time complexities of reconstructions by hardware as well as software, and the hardware complexity in terms of the number of gates in the logical circuit added to each PE among the other methods.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - An Efficient Method for Reconfiguring the 1 1/2 Track-Switch Mesh Array
T2 - IEICE TRANSACTIONS on Information
SP - 1545
EP - 1553
AU - Tadayoshi HORITA
AU - Itsuo TAKANAMI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 1999
AB - As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer scale integration is growing. The major problem for the case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations. Various strategies to restructure the faulty physical system into the fault-free target logical system are described in the literature [1]-[5]. In this paper, we propose an efficient approximate method which can reconstruct the 1 1/2 track-switch mesh arrays with faulty PEs using hardware as well as software. A logical circuit added to each PE and a network connecting the circuits are used to decide spare PEs which compensate for faulty PEs. The hardware compexity of each circuit is much less than that of a PE where the size of each additional circuit is independent of array sizes and constant. By using the exclusive hardware scheme, a built-in self-reconfigurable system without using a host computer is realizable and the time for reconfiguring arrays becomes very short. The simulation result of the performance of the method shows that the reconstructing efficiency of our algorithm is a little less than those of the exaustive and Shigei's ones [6] and [7], but much better than that of the neural one [3]. We also compare the time complexities of reconstructions by hardware as well as software, and the hardware complexity in terms of the number of gates in the logical circuit added to each PE among the other methods.
ER -