The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
우리는 3 트랙 스위치를 사용하는 내결함성 3D 프로세서 어레이 모델을 제안합니다. 예비 프로세서는 4D 어레이의 반대쪽 두 표면에 배치됩니다. 결함 보상 프로세스는 결함이 있는 프로세서에서 표면의 예비 프로세서로 연속 직선(보상 경로라고 함)의 프로세서를 이동하여 수행됩니다. 보상 경로가 서로 Near-Miss 관계에 있는 것은 허용되지 않습니다. 그런 다음 결함을 보상한 후 3D 메시 토폴로지를 보존하려면 3개 상태만 있는 스위치가 필요합니다. 결함이 있는 3차원 메시 배열을 하드웨어로 재구성하기 위한 편리한 형태의 알고리즘을 제공합니다. 알고리즘은 다항식 시간에 3D 메시 배열을 재구성할 수 있습니다. 컴퓨터 시뮬레이션을 통해 알고리즘에 따른 재구성의 효율성을 표현하는 배열의 생존율과 신뢰성을 보여줍니다. 보상 경로 간 Near-Miss 관계를 허용하지만 하드웨어 오버헤드가 XNUMX선을 사용하는 제안 모델의 거의 두 배인 복선을 사용하는 모델의 신뢰도를 비교합니다. 마지막으로 알고리즘의 하드웨어 구현을 위한 논리회로를 설계한다. 회로를 사용하면 호스트 컴퓨터의 도움 없이 매우 빠르게 재구성이 완료되는 내장된 자체 재구성 가능한 XNUMXD 메시 어레이를 구성할 수 있습니다.
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Itsuo TAKANAMI, Tadayoshi HORITA, "A Built-in Self-Reconfigurable Scheme for 3D Mesh Arrays" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 12, pp. 1554-1562, December 1999, doi: .
Abstract: We propose a model for fault tolerant 3D processor arrays using one-and-half track switches. Spare processors are laid on the two opposite surfaces of the 3D array. The fault compensation process is performed by shifting processors on a continuous straight line (called compensation path) from a faulty processor to a spare on the surfaces. It is not allowed that compensantion paths are in the near-miss relation each other. Then, switches with only 4 states are needed to preserve the 3D mesh topology after compensating for faults. We give an algorithm in a convenient form for reconfiguring by hardware the 3D mesh arrays with faults. The algorithm can reconfigure the 3D mesh arrays in polynomial time. By computer simulation, we show the survival rates and the reliabilities of arrays which express the efficiencies of reconfiguration according to the algorithm. The reliabilities are compared with those of the model using double tracks for which the near-miss relation among compensation paths is allowed, but whose hardware overhead is almost double of that of the proposed model using one-and-half track. Finally, we design a logical circuit for hardware realization of the algorithm. Using the circuit, we can construct such a built-in self-reconfigurable 3D mesh array that the reconfiguration is done very quickly without an aid of a host computer.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_12_1554/_p
부
@ARTICLE{e82-d_12_1554,
author={Itsuo TAKANAMI, Tadayoshi HORITA, },
journal={IEICE TRANSACTIONS on Information},
title={A Built-in Self-Reconfigurable Scheme for 3D Mesh Arrays},
year={1999},
volume={E82-D},
number={12},
pages={1554-1562},
abstract={We propose a model for fault tolerant 3D processor arrays using one-and-half track switches. Spare processors are laid on the two opposite surfaces of the 3D array. The fault compensation process is performed by shifting processors on a continuous straight line (called compensation path) from a faulty processor to a spare on the surfaces. It is not allowed that compensantion paths are in the near-miss relation each other. Then, switches with only 4 states are needed to preserve the 3D mesh topology after compensating for faults. We give an algorithm in a convenient form for reconfiguring by hardware the 3D mesh arrays with faults. The algorithm can reconfigure the 3D mesh arrays in polynomial time. By computer simulation, we show the survival rates and the reliabilities of arrays which express the efficiencies of reconfiguration according to the algorithm. The reliabilities are compared with those of the model using double tracks for which the near-miss relation among compensation paths is allowed, but whose hardware overhead is almost double of that of the proposed model using one-and-half track. Finally, we design a logical circuit for hardware realization of the algorithm. Using the circuit, we can construct such a built-in self-reconfigurable 3D mesh array that the reconfiguration is done very quickly without an aid of a host computer.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - A Built-in Self-Reconfigurable Scheme for 3D Mesh Arrays
T2 - IEICE TRANSACTIONS on Information
SP - 1554
EP - 1562
AU - Itsuo TAKANAMI
AU - Tadayoshi HORITA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 1999
AB - We propose a model for fault tolerant 3D processor arrays using one-and-half track switches. Spare processors are laid on the two opposite surfaces of the 3D array. The fault compensation process is performed by shifting processors on a continuous straight line (called compensation path) from a faulty processor to a spare on the surfaces. It is not allowed that compensantion paths are in the near-miss relation each other. Then, switches with only 4 states are needed to preserve the 3D mesh topology after compensating for faults. We give an algorithm in a convenient form for reconfiguring by hardware the 3D mesh arrays with faults. The algorithm can reconfigure the 3D mesh arrays in polynomial time. By computer simulation, we show the survival rates and the reliabilities of arrays which express the efficiencies of reconfiguration according to the algorithm. The reliabilities are compared with those of the model using double tracks for which the near-miss relation among compensation paths is allowed, but whose hardware overhead is almost double of that of the proposed model using one-and-half track. Finally, we design a logical circuit for hardware realization of the algorithm. Using the circuit, we can construct such a built-in self-reconfigurable 3D mesh array that the reconfiguration is done very quickly without an aid of a host computer.
ER -