The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 문서에서는 REMARC(Reconfigurable Multimedia Array Coprocessor)라는 새로운 재구성 가능한 프로세서 아키텍처에 대해 설명합니다. REMARC는 메인 RISC 프로세서에 긴밀하게 연결된 소형 어레이 프로세서입니다. 이는 글로벌 제어 장치와 나노 프로세서라고 불리는 64개의 16비트 프로세서로 구성됩니다. REMARC는 비디오 압축, 압축 해제 및 이미지 처리와 같은 멀티미디어 애플리케이션을 가속화하도록 설계되었습니다. 이러한 애플리케이션은 일반적으로 8비트 또는 16비트 데이터를 사용하므로 각 나노 프로세서는 다른 재구성 가능한 보조 프로세서보다 훨씬 넓은 16비트 데이터 경로를 갖습니다. 우리는 REMARC와 여러 가지 현실적인 응용 프로그램, DES 암호화, MPEG-2 디코딩 및 MPEG-2 인코딩을 위한 프로그래밍 환경을 개발했습니다. REMARC는 이러한 멀티미디어 애플리케이션에 나타나는 다양한 병렬 알고리즘을 구현할 수 있습니다. 예를 들어, REMARC는 MPEG-2 디코딩의 모션 보상을 위한 멀티미디어 명령어 확장과 유사한 SIMD 유형 명령어를 구현할 수 있습니다. 또한 MPEG-2 인코딩의 모션 추정에 나타나는 수축기 알고리즘과 같은 고도로 파이프라인화된 알고리즘도 효율적으로 구현할 수 있습니다. REMARC는 단일 이슈 프로세서 또는 2.3 이슈 수퍼스칼라 프로세서인 기본 프로세서에 비해 21.2~2배의 속도 향상을 달성합니다. 또한 멀티미디어 명령어 확장과의 성능을 비교합니다. REMARC는 더 많은 처리 리소스를 사용하여 멀티미디어 명령어 확장보다 더 높은 성능을 달성할 수 있습니다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Takashi MIYAMORI, Kunle OLUKOTUN, "REMARC: Reconfigurable Multimedia Array Coprocessor" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 2, pp. 389-397, February 1999, doi: .
Abstract: This paper describes a new reconfigurable processor architecture called REMARC (Reconfigurable Multimedia Array Coprocessor). REMARC is a small array processor that is tightly coupled to a main RISC processor. It consists of a global control unit and 64 16-bit processors called nano processors. REMARC is designed to accelerate multimedia applications, such as video compression, decompression, and image processing. These applications typically use 8-bit or 16-bit data therefore, each nano processor has a 16-bit datapath that is much wider than those of other reconfigurable coprocessors. We have developed a programming environment for REMARC and several realistic application programs, DES encryption, MPEG-2 decoding, and MPEG-2 encoding. REMARC can implement various parallel algorithms which appear in these multimedia applications. For instance, REMARC can implement SIMD type instructions similar to multimedia instruction extensions for motion compensation of the MPEG-2 decoding. Furthermore, the highly pipelined algorithms, like systolic algorithms, which appear in motion estimation of the MPEG-2 encoding can also be implemented efficiently. REMARC achieves speedups ranging from a factor of 2.3 to 21.2 over the base processor which is a single issue processor or 2-issue superscalar processor. We also compare its performance with multimedia instruction extensions. Using more processing resources, REMARC can achieve higher performance than multimedia instruction extensions.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_2_389/_p
부
@ARTICLE{e82-d_2_389,
author={Takashi MIYAMORI, Kunle OLUKOTUN, },
journal={IEICE TRANSACTIONS on Information},
title={REMARC: Reconfigurable Multimedia Array Coprocessor},
year={1999},
volume={E82-D},
number={2},
pages={389-397},
abstract={This paper describes a new reconfigurable processor architecture called REMARC (Reconfigurable Multimedia Array Coprocessor). REMARC is a small array processor that is tightly coupled to a main RISC processor. It consists of a global control unit and 64 16-bit processors called nano processors. REMARC is designed to accelerate multimedia applications, such as video compression, decompression, and image processing. These applications typically use 8-bit or 16-bit data therefore, each nano processor has a 16-bit datapath that is much wider than those of other reconfigurable coprocessors. We have developed a programming environment for REMARC and several realistic application programs, DES encryption, MPEG-2 decoding, and MPEG-2 encoding. REMARC can implement various parallel algorithms which appear in these multimedia applications. For instance, REMARC can implement SIMD type instructions similar to multimedia instruction extensions for motion compensation of the MPEG-2 decoding. Furthermore, the highly pipelined algorithms, like systolic algorithms, which appear in motion estimation of the MPEG-2 encoding can also be implemented efficiently. REMARC achieves speedups ranging from a factor of 2.3 to 21.2 over the base processor which is a single issue processor or 2-issue superscalar processor. We also compare its performance with multimedia instruction extensions. Using more processing resources, REMARC can achieve higher performance than multimedia instruction extensions.},
keywords={},
doi={},
ISSN={},
month={February},}
부
TY - JOUR
TI - REMARC: Reconfigurable Multimedia Array Coprocessor
T2 - IEICE TRANSACTIONS on Information
SP - 389
EP - 397
AU - Takashi MIYAMORI
AU - Kunle OLUKOTUN
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 1999
AB - This paper describes a new reconfigurable processor architecture called REMARC (Reconfigurable Multimedia Array Coprocessor). REMARC is a small array processor that is tightly coupled to a main RISC processor. It consists of a global control unit and 64 16-bit processors called nano processors. REMARC is designed to accelerate multimedia applications, such as video compression, decompression, and image processing. These applications typically use 8-bit or 16-bit data therefore, each nano processor has a 16-bit datapath that is much wider than those of other reconfigurable coprocessors. We have developed a programming environment for REMARC and several realistic application programs, DES encryption, MPEG-2 decoding, and MPEG-2 encoding. REMARC can implement various parallel algorithms which appear in these multimedia applications. For instance, REMARC can implement SIMD type instructions similar to multimedia instruction extensions for motion compensation of the MPEG-2 decoding. Furthermore, the highly pipelined algorithms, like systolic algorithms, which appear in motion estimation of the MPEG-2 encoding can also be implemented efficiently. REMARC achieves speedups ranging from a factor of 2.3 to 21.2 over the base processor which is a single issue processor or 2-issue superscalar processor. We also compare its performance with multimedia instruction extensions. Using more processing resources, REMARC can achieve higher performance than multimedia instruction extensions.
ER -