The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
사용 가능한 통계적 왜곡 모델은 균형이 잘 잡힌 H-트리의 예상 클록 왜곡을 추정하는 데 너무 보수적입니다. 균형이 잘 잡힌 H-트리의 클록 스큐와 최대 클록 지연 모두의 예상 값과 분산을 정확하게 추정하기 위한 새로운 폐쇄형 표현식이 제공됩니다. 새로운 모델을 기반으로 웨이퍼 규모 H-트리 클럭 네트워크의 클럭 주기 최적화가 기존 클럭킹 모드와 파이프라인 클럭킹 모드 모두에서 조사되었습니다. 기존의 클로킹 모드를 사용할 때 웨이퍼 스케일 H-트리의 클록 주기 최적화는 영역 제한과 전력 제한 모두에서 예상되는 최대 클록 지연을 최소화하는 것으로 나타났습니다. 반면, 파이프라인 클로킹 모드를 고려하면 전력 제한 하에서 예상되는 클럭 스큐를 최소화하는 수준으로 최적화가 축소됩니다. 본 논문에서 얻은 결과는 웨이퍼 규모 H-트리 클럭 분배 네트워크의 최적화 설계에 매우 유용합니다.
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부
Xiaohong JIANG, Susumu HORIGUCHI, "Statistical Skew Modeling and Clock Period Optimization of Wafer Scale H-Tree Clock Distribution Network" in IEICE TRANSACTIONS on Information,
vol. E84-D, no. 11, pp. 1476-1485, November 2001, doi: .
Abstract: Available statistical skew models are too conservative in estimating the expected clock skew of a well-balanced H-tree. New closed form expressions are presented for accurately estimating the expected values and the variances of both the clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimizations of wafer scale H-tree clock network are investigated under both conventional clocking mode and pipelined clocking mode. It is found that when the conventional clocking mode is used, clock period optimization of wafer scale H-tree is reduced to the minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction. The results obtained in this paper are very useful in the optimization design of wafer scale H-tree clock distribution networks.
URL: https://global.ieice.org/en_transactions/information/10.1587/e84-d_11_1476/_p
부
@ARTICLE{e84-d_11_1476,
author={Xiaohong JIANG, Susumu HORIGUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={Statistical Skew Modeling and Clock Period Optimization of Wafer Scale H-Tree Clock Distribution Network},
year={2001},
volume={E84-D},
number={11},
pages={1476-1485},
abstract={Available statistical skew models are too conservative in estimating the expected clock skew of a well-balanced H-tree. New closed form expressions are presented for accurately estimating the expected values and the variances of both the clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimizations of wafer scale H-tree clock network are investigated under both conventional clocking mode and pipelined clocking mode. It is found that when the conventional clocking mode is used, clock period optimization of wafer scale H-tree is reduced to the minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction. The results obtained in this paper are very useful in the optimization design of wafer scale H-tree clock distribution networks.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - Statistical Skew Modeling and Clock Period Optimization of Wafer Scale H-Tree Clock Distribution Network
T2 - IEICE TRANSACTIONS on Information
SP - 1476
EP - 1485
AU - Xiaohong JIANG
AU - Susumu HORIGUCHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E84-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2001
AB - Available statistical skew models are too conservative in estimating the expected clock skew of a well-balanced H-tree. New closed form expressions are presented for accurately estimating the expected values and the variances of both the clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimizations of wafer scale H-tree clock network are investigated under both conventional clocking mode and pipelined clocking mode. It is found that when the conventional clocking mode is used, clock period optimization of wafer scale H-tree is reduced to the minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction. The results obtained in this paper are very useful in the optimization design of wafer scale H-tree clock distribution networks.
ER -