The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 처리 블록으로 다수의 단순화된 ALU(sALU)로 구성된 새로운 아키텍처 기반 마이크로프로세서인 DPPP(Dynamic Programmable Parallel Processor)에 대해 설명합니다. 모든 sALU는 물리적 배선 대신 코드 일치를 통해 가상으로 연결을 설정함으로써 완벽한 라우팅 유연성을 제공하는 코드 분할 다중 액세스 버스 인터페이스를 통해 상호 연결됩니다. 이 기능은 높은 병렬성과 내결함성을 달성하기 위해 더욱 활용됩니다. 기존 제작 기반 기술의 한계나 예비 부품 제공 없이 높은 내결함성을 구현합니다. DPPP의 또 다른 특징은 제공된 사용자 자동 프로그램 인터페이스를 사용하여 숫자 공식 입력을 컴파일하여 구성할 수 있으므로 간단한 프로그래밍 가능성입니다. 제안된 아키텍처를 기반으로 한 프로토타입 칩이 4.5mm 크기로 구현되었습니다.
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부
Boon-Keat TAN, Ryuji YOSHIMURA, Toshimasa MATSUOKA, Kenji TANIGUCHI, "Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface" in IEICE TRANSACTIONS on Information,
vol. E84-D, no. 11, pp. 1521-1527, November 2001, doi: .
Abstract: This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm
URL: https://global.ieice.org/en_transactions/information/10.1587/e84-d_11_1521/_p
부
@ARTICLE{e84-d_11_1521,
author={Boon-Keat TAN, Ryuji YOSHIMURA, Toshimasa MATSUOKA, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface},
year={2001},
volume={E84-D},
number={11},
pages={1521-1527},
abstract={This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface
T2 - IEICE TRANSACTIONS on Information
SP - 1521
EP - 1527
AU - Boon-Keat TAN
AU - Ryuji YOSHIMURA
AU - Toshimasa MATSUOKA
AU - Kenji TANIGUCHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E84-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2001
AB - This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm
ER -