The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
유전자 알고리즘을 이용한 커널 기반의 패턴인식 하드웨어와 그 설계 방법론을 제안한다. 제안된 설계 방법론에서는 패턴 데이터를 진리표로 변환하고 진리표를 진화시켜 패턴 인식을 위한 판별 함수의 커널을 표현합니다. 진화된 진리표는 논리 회로로 합성됩니다. 이러한 데이터 직접 구현 접근 방식으로 인해 부동 소수점 수치 회로가 필요하지 않으며 패턴 데이터 세트의 고유 병렬성이 회로에 내장됩니다. 결과적으로, 허용 가능한 작은 회로 크기로 고속 인식 시스템을 구현할 수 있습니다. 우리는 이 방법론을 이미지 인식 및 소나 스펙트럼 인식 작업에 적용하여 새로 개발된 FPGA 기반 재구성 가능한 패턴 인식 보드에 구현했습니다. 개발된 시스템은 기존 접근 방식보다 더 높은 인식 정확도와 훨씬 빠른 처리 속도를 보여줍니다.
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Moritoshi YASUNAGA, Taro NAKAMURA, Ikuo YOSHIHARA, Jung Hwan KIM, "The Kernel-Based Pattern Recognition System Designed by Genetic Algorithms" in IEICE TRANSACTIONS on Information,
vol. E84-D, no. 11, pp. 1528-1539, November 2001, doi: .
Abstract: We propose the kernel-based pattern recognition hardware and its design methodology using the genetic algorithm. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are evolved to represent kernels in the discrimination functions for pattern recognition. The evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the pattern data set is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the image recognition and the sonar spectrum recognition tasks, and implemented them onto the newly developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates higher recognition accuracy and much faster processing speed than the conventional approaches.
URL: https://global.ieice.org/en_transactions/information/10.1587/e84-d_11_1528/_p
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@ARTICLE{e84-d_11_1528,
author={Moritoshi YASUNAGA, Taro NAKAMURA, Ikuo YOSHIHARA, Jung Hwan KIM, },
journal={IEICE TRANSACTIONS on Information},
title={The Kernel-Based Pattern Recognition System Designed by Genetic Algorithms},
year={2001},
volume={E84-D},
number={11},
pages={1528-1539},
abstract={We propose the kernel-based pattern recognition hardware and its design methodology using the genetic algorithm. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are evolved to represent kernels in the discrimination functions for pattern recognition. The evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the pattern data set is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the image recognition and the sonar spectrum recognition tasks, and implemented them onto the newly developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates higher recognition accuracy and much faster processing speed than the conventional approaches.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - The Kernel-Based Pattern Recognition System Designed by Genetic Algorithms
T2 - IEICE TRANSACTIONS on Information
SP - 1528
EP - 1539
AU - Moritoshi YASUNAGA
AU - Taro NAKAMURA
AU - Ikuo YOSHIHARA
AU - Jung Hwan KIM
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E84-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2001
AB - We propose the kernel-based pattern recognition hardware and its design methodology using the genetic algorithm. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are evolved to represent kernels in the discrimination functions for pattern recognition. The evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the pattern data set is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the image recognition and the sonar spectrum recognition tasks, and implemented them onto the newly developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates higher recognition accuracy and much faster processing speed than the conventional approaches.
ER -