The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 계층적 테스트 생성이 적용 가능한 DFT를 적용한 RTL 데이터 경로 회로에 대해 압축된 테스트 테이블을 사용한 테스트 생성 방법과 압축된 테스트 계획 테이블을 사용한 테스트 생성 방법을 제안합니다. 또한, 압축된 테스트 계획 테이블 생성을 위한 휴리스틱 알고리즘을 제안한다. 제안된 방법은 기존의 계층적 테스트 생성 방법에 비해 일부 RTL 데이터 경로 회로의 테스트 길이를 단축할 수 있습니다.
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Toshinori HOSOKAWA, Hiroshi DATE, Michiaki MURAOKA, "Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 10, pp. 1474-1482, October 2002, doi: .
Abstract: This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_10_1474/_p
부
@ARTICLE{e85-d_10_1474,
author={Toshinori HOSOKAWA, Hiroshi DATE, Michiaki MURAOKA, },
journal={IEICE TRANSACTIONS on Information},
title={Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits},
year={2002},
volume={E85-D},
number={10},
pages={1474-1482},
abstract={This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.},
keywords={},
doi={},
ISSN={},
month={October},}
부
TY - JOUR
TI - Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 1474
EP - 1482
AU - Toshinori HOSOKAWA
AU - Hiroshi DATE
AU - Michiaki MURAOKA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2002
AB - This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.
ER -