The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
An n-고착된 오류에 대한 감지 테스트는 지연 오류 테스트뿐만 아니라 모델링되지 않은 오류 감지에도 사용할 수 있습니다. 우리는 하이브리드 BIST 회로를 개발했습니다. 즉, 부분 회전이 있는 시프트 레지스터와 ATPG 벡터에서 테스트 벡터를 선택하는 절차로 구성된 방법입니다. 이 테스트 방법은 높은 정체 오류 범위로 속도 테스트를 수행할 수 있습니다. at-speed 테스트 중에는 저속 테스터를 사용하여 ATPG 벡터의 하위 집합이 입력됩니다. ISCAS'85, ISCAS'89 및 ITC'99 회로에 대한 컴퓨터 시뮬레이션이 수행됩니다. n = 1, 2, 3, 5, 10, 15. 시뮬레이션 결과, ATPG 벡터에 비해 테스트 벡터의 양을 52.3%~0.9%까지 줄일 수 있음을 보여주었다. 결과적으로 제안된 방법은 at-speed 테스트 비용을 절감할 수 있다.
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Kenichi ICHINO, Takeshi ASAKAWA, Satoshi FUKUMOTO, Kazuhiko IWASAKI, Seiji KAJIHARA, "Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 10, pp. 1490-1497, October 2002, doi: .
Abstract: An n-detection testing for stuck-at faults can be used not only for delay fault testing but also for detection of unmodeled faults. We have developed a hybrid BIST circuit; that is, a method consisting of a shift register with partial rotation and a procedure that selects test vectors from ATPG ones. This testing method can perform at-speed testing with high stuck-at fault coverage. During the at-speed testing, a subset of the ATPG vectors is input by using a low-speed tester. Computer simulations on ISCAS'85, ISCAS'89, and ITC'99 circuits are conducted for n = 1, 2, 3, 5, 10, and 15. The simulation results show that the amount of test vectors can be reduced to ranging from 52.3% to 0.9% in comparison with that of the ATPG vectors. As a result, the proposed method can reduce the cost of at-speed testing.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_10_1490/_p
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@ARTICLE{e85-d_10_1490,
author={Kenichi ICHINO, Takeshi ASAKAWA, Satoshi FUKUMOTO, Kazuhiko IWASAKI, Seiji KAJIHARA, },
journal={IEICE TRANSACTIONS on Information},
title={Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan},
year={2002},
volume={E85-D},
number={10},
pages={1490-1497},
abstract={An n-detection testing for stuck-at faults can be used not only for delay fault testing but also for detection of unmodeled faults. We have developed a hybrid BIST circuit; that is, a method consisting of a shift register with partial rotation and a procedure that selects test vectors from ATPG ones. This testing method can perform at-speed testing with high stuck-at fault coverage. During the at-speed testing, a subset of the ATPG vectors is input by using a low-speed tester. Computer simulations on ISCAS'85, ISCAS'89, and ITC'99 circuits are conducted for n = 1, 2, 3, 5, 10, and 15. The simulation results show that the amount of test vectors can be reduced to ranging from 52.3% to 0.9% in comparison with that of the ATPG vectors. As a result, the proposed method can reduce the cost of at-speed testing.},
keywords={},
doi={},
ISSN={},
month={October},}
부
TY - JOUR
TI - Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan
T2 - IEICE TRANSACTIONS on Information
SP - 1490
EP - 1497
AU - Kenichi ICHINO
AU - Takeshi ASAKAWA
AU - Satoshi FUKUMOTO
AU - Kazuhiko IWASAKI
AU - Seiji KAJIHARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2002
AB - An n-detection testing for stuck-at faults can be used not only for delay fault testing but also for detection of unmodeled faults. We have developed a hybrid BIST circuit; that is, a method consisting of a shift register with partial rotation and a procedure that selects test vectors from ATPG ones. This testing method can perform at-speed testing with high stuck-at fault coverage. During the at-speed testing, a subset of the ATPG vectors is input by using a low-speed tester. Computer simulations on ISCAS'85, ISCAS'89, and ITC'99 circuits are conducted for n = 1, 2, 3, 5, 10, and 15. The simulation results show that the amount of test vectors can be reduced to ranging from 52.3% to 0.9% in comparison with that of the ATPG vectors. As a result, the proposed method can reduce the cost of at-speed testing.
ER -