The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
단일 칩에 이기종 다중 프로세서를 위한 디버그 시스템이 개발되었습니다. 시스템은 칩에 통합된 디버그 인터페이스 회로, 칩과 PC 사이의 인터페이스 회로 기판, PC에 구현된 디버그 소프트웨어로 구성됩니다. 이 디버그 시스템은 원래의 비디오 프로세서 코어, RISC 프로세서 및 DSP를 포함하는 멀티미디어 통신 프로세서용으로 설계되었습니다. RISC 프로세서는 원래의 비디오 프로세서와 기타 하드웨어 기능을 포함하는 비디오 처리 장치를 제어합니다. 디버그 모드에 있는 동안 외부 디버거는 RISC 프로세서와 동일한 방식으로 비디오 처리 장치를 제어할 수 있습니다. JTAG 기반 인터페이스 회로에는 명령, 주소, 기록할 데이터 등을 위한 버스 트랜잭션용 레지스터와 버스 트랜잭션 시퀀서가 포함되어 있습니다. 실제로 이 시스템은 RISC 프로세서와 동일한 버스 트랜잭션 제어를 실현할 수 있습니다. 제안된 디버그 시스템을 적용하면 RISC 처리 장치와 비디오 처리 장치의 동시 디버그가 구현될 수 있다. 이를 통해 문제를 보다 신속하게 조사할 수 있으며 디버깅에 필요한 총 시간이 효율적으로 단축됩니다. 이 기술이 없으면 칩을 디버깅하는 데 약 19주가 소요되는 반면, 이 기술을 사용하면 디버깅을 9주 만에 완료할 수 있습니다.
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Noriyuki MINEGISHI, Ken-ichi ASANO, Hirokazu SUZUKI, Keisuke OKADA, Takashi KAN, "A Debug System for Heterogeneous Multiple Processors in a Single Chip for Multimedia Communication" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 10, pp. 1571-1578, October 2002, doi: .
Abstract: A debug system for heterogeneous multiple processors in a single chip has been developed. The system consists of the debug interface circuit integrated on the chip, the interface circuit board between the chip and PC, and the debug software implemented on a PC. This debug system has been designed for a multimedia communication processor, which includes an original video processor core, a RISC processor, and a DSP. The RISC processor controls the Video Processing Unit that includes an original video processor and other hardware functions. While in debug mode, the external debugger can control the Video Processing Unit in the same manner as the RISC processor. The JTAG based interface circuit contains registers for bus transaction for command, address, and data to be written, etc. and a bus transaction sequencer. In fact, this system can realize the same bus transaction control as the RISC processor's. By applying proposed debug system, simultaneous debug of the RISC Processing Unit and the Video Processing Unit can be realized. This allows problems to be investigated more quickly and the total time required for debugging is efficiently reduced. Without this technology an estimated 19 weeks is required to debug the chip, whereas use of this technology allowed debugging to be completed in 9 weeks.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_10_1571/_p
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@ARTICLE{e85-d_10_1571,
author={Noriyuki MINEGISHI, Ken-ichi ASANO, Hirokazu SUZUKI, Keisuke OKADA, Takashi KAN, },
journal={IEICE TRANSACTIONS on Information},
title={A Debug System for Heterogeneous Multiple Processors in a Single Chip for Multimedia Communication},
year={2002},
volume={E85-D},
number={10},
pages={1571-1578},
abstract={A debug system for heterogeneous multiple processors in a single chip has been developed. The system consists of the debug interface circuit integrated on the chip, the interface circuit board between the chip and PC, and the debug software implemented on a PC. This debug system has been designed for a multimedia communication processor, which includes an original video processor core, a RISC processor, and a DSP. The RISC processor controls the Video Processing Unit that includes an original video processor and other hardware functions. While in debug mode, the external debugger can control the Video Processing Unit in the same manner as the RISC processor. The JTAG based interface circuit contains registers for bus transaction for command, address, and data to be written, etc. and a bus transaction sequencer. In fact, this system can realize the same bus transaction control as the RISC processor's. By applying proposed debug system, simultaneous debug of the RISC Processing Unit and the Video Processing Unit can be realized. This allows problems to be investigated more quickly and the total time required for debugging is efficiently reduced. Without this technology an estimated 19 weeks is required to debug the chip, whereas use of this technology allowed debugging to be completed in 9 weeks.},
keywords={},
doi={},
ISSN={},
month={October},}
부
TY - JOUR
TI - A Debug System for Heterogeneous Multiple Processors in a Single Chip for Multimedia Communication
T2 - IEICE TRANSACTIONS on Information
SP - 1571
EP - 1578
AU - Noriyuki MINEGISHI
AU - Ken-ichi ASANO
AU - Hirokazu SUZUKI
AU - Keisuke OKADA
AU - Takashi KAN
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2002
AB - A debug system for heterogeneous multiple processors in a single chip has been developed. The system consists of the debug interface circuit integrated on the chip, the interface circuit board between the chip and PC, and the debug software implemented on a PC. This debug system has been designed for a multimedia communication processor, which includes an original video processor core, a RISC processor, and a DSP. The RISC processor controls the Video Processing Unit that includes an original video processor and other hardware functions. While in debug mode, the external debugger can control the Video Processing Unit in the same manner as the RISC processor. The JTAG based interface circuit contains registers for bus transaction for command, address, and data to be written, etc. and a bus transaction sequencer. In fact, this system can realize the same bus transaction control as the RISC processor's. By applying proposed debug system, simultaneous debug of the RISC Processing Unit and the Video Processing Unit can be realized. This allows problems to be investigated more quickly and the total time required for debugging is efficiently reduced. Without this technology an estimated 19 weeks is required to debug the chip, whereas use of this technology allowed debugging to be completed in 9 weeks.
ER -