The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
3차원 적층형 IC의 다이와 입출력 핀 간의 배선에서 발생하는 개방형 결함을 검출하기 위한 테스트 가능성을 위한 설계 방법과 전기적 배선 테스트 방법이 제안된다. 설계 방법의 일부로 nMOS와 다이오드가 각 입력 상호 연결에 추가됩니다. 테스트 방법은 테스트할 상호 연결을 통해 흐르는 대기 전류를 측정하는 것을 기반으로 합니다. 테스트 가능성은 SPICE 시뮬레이션과 실험을 통해 검사됩니다. 테스트 방법을 통해 1MHz의 실험 테스트 속도에서 새로 설계된 다이의 상호 연결에서 발생하는 개방형 결함을 감지할 수 있었습니다. 시뮬레이션 결과, 279psec의 추가 지연을 발생시키는 개방형 결함은 논리적 오류를 생성하지 않는 개방형 결함 외에 200MHz의 테스트 속도에서 테스트 방법으로 검출할 수 있는 것으로 나타났습니다.
Fara ASHIKIN
Tokushima University,Universiti Teknikal Malaysia Melaka
Masaki HASHIZUME
Tokushima University
Hiroyuki YOTSUYANAGI
Tokushima University
Shyue-Kung LU
National Taiwan University of Science and Technology
Zvi ROTH
Florida Atlantic University
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Fara ASHIKIN, Masaki HASHIZUME, Hiroyuki YOTSUYANAGI, Shyue-Kung LU, Zvi ROTH, "A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs" in IEICE TRANSACTIONS on Information,
vol. E101-D, no. 8, pp. 2053-2063, August 2018, doi: 10.1587/transinf.2018EDP7093.
Abstract: A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2018EDP7093/_p
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@ARTICLE{e101-d_8_2053,
author={Fara ASHIKIN, Masaki HASHIZUME, Hiroyuki YOTSUYANAGI, Shyue-Kung LU, Zvi ROTH, },
journal={IEICE TRANSACTIONS on Information},
title={A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs},
year={2018},
volume={E101-D},
number={8},
pages={2053-2063},
abstract={A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.},
keywords={},
doi={10.1587/transinf.2018EDP7093},
ISSN={1745-1361},
month={August},}
부
TY - JOUR
TI - A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs
T2 - IEICE TRANSACTIONS on Information
SP - 2053
EP - 2063
AU - Fara ASHIKIN
AU - Masaki HASHIZUME
AU - Hiroyuki YOTSUYANAGI
AU - Shyue-Kung LU
AU - Zvi ROTH
PY - 2018
DO - 10.1587/transinf.2018EDP7093
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E101-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2018
AB - A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.
ER -