The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
영상에서 고정밀도 직선 추출을 실현하는 허프 변환(HT)을 적용하면 효율적인 차선 검출이 가능할 것으로 기대됩니다. 실제 애플리케이션에서 HT 하드웨어 구현의 주요 과제는 정확도 극대화, 전력 손실 감소 및 실시간 요구 사항 간의 균형 최적화입니다. 우리는 병렬화된 투표 절차, 로컬 최대 알고리즘 및 FPGA 프로토타입 구현을 갖춘 도로 차선 감지를 위한 HT 하드웨어 아키텍처를 보고합니다. 전역 설계의 병렬화는 Hough 공간의 θ 값 이산화를 기반으로 실현됩니다. 원본 비디오 프레임의 에지 검출, 허프 공간의 특징적인 에지 픽셀 값(ρ,θ) 계산, 병렬 로컬 최대 기반 기반의 각 (ρ,θ) 쌍에 대한 투표 절차를 위해 1개의 주요 하드웨어 모듈이 개발되었습니다. 검출된 직선을 결정하기 위해 Hough 공간에서 최고 투표점 추출. Cyclone II FPGA 장치를 사용하여 저가형 DE135 플랫폼에서 실시간 도로 차선 감지를 위한 프로토타입 시스템 구현이 가능한 것으로 확인되었습니다. VGA(640x480) 프레임에 대해 평균 50프레임/초의 감지 속도가 XNUMXMHz 작동 주파수에서 달성되었습니다.
Jungang GUAN
Hiroshima University
Fengwei AN
Hiroshima University
Xiangyu ZHANG
Hiroshima University
Lei CHEN
Hiroshima University
Hans Jürgen MATTAUSCH
Hiroshima University
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Jungang GUAN, Fengwei AN, Xiangyu ZHANG, Lei CHEN, Hans Jürgen MATTAUSCH, "Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm" in IEICE TRANSACTIONS on Information,
vol. E102-D, no. 6, pp. 1171-1182, June 2019, doi: 10.1587/transinf.2018EDP7279.
Abstract: Efficient road-lane detection is expected to be achievable by application of the Hough transform (HT) which realizes high-accuracy straight-line extraction from images. The main challenge for HT-hardware implementation in actual applications is the trade-off optimization between accuracy maximization, power-dissipation reduction and real-time requirements. We report a HT-hardware architecture for road-lane detection with parallelized voting procedure, local maximum algorithm and FPGA-prototype implementation. Parallelization of the global design is realized on the basis of θ-value discretization in the Hough space. Four major hardware modules are developed for edge detection in the original video frames, computation of the characteristic edge-pixel values (ρ,θ) in Hough-space, voting procedure for each (ρ,θ) pair with parallel local-maximum-based peak voting-point extraction in Hough space to determine the detected straight lines. Implementation of a prototype system for real-time road-lane detection on a low-cost DE1 platform with a Cyclone II FPGA device was verified to be possible. An average detection speed of 135 frames/s for VGA (640x480)-frames was achieved at 50 MHz working frequency.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2018EDP7279/_p
부
@ARTICLE{e102-d_6_1171,
author={Jungang GUAN, Fengwei AN, Xiangyu ZHANG, Lei CHEN, Hans Jürgen MATTAUSCH, },
journal={IEICE TRANSACTIONS on Information},
title={Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm},
year={2019},
volume={E102-D},
number={6},
pages={1171-1182},
abstract={Efficient road-lane detection is expected to be achievable by application of the Hough transform (HT) which realizes high-accuracy straight-line extraction from images. The main challenge for HT-hardware implementation in actual applications is the trade-off optimization between accuracy maximization, power-dissipation reduction and real-time requirements. We report a HT-hardware architecture for road-lane detection with parallelized voting procedure, local maximum algorithm and FPGA-prototype implementation. Parallelization of the global design is realized on the basis of θ-value discretization in the Hough space. Four major hardware modules are developed for edge detection in the original video frames, computation of the characteristic edge-pixel values (ρ,θ) in Hough-space, voting procedure for each (ρ,θ) pair with parallel local-maximum-based peak voting-point extraction in Hough space to determine the detected straight lines. Implementation of a prototype system for real-time road-lane detection on a low-cost DE1 platform with a Cyclone II FPGA device was verified to be possible. An average detection speed of 135 frames/s for VGA (640x480)-frames was achieved at 50 MHz working frequency.},
keywords={},
doi={10.1587/transinf.2018EDP7279},
ISSN={1745-1361},
month={June},}
부
TY - JOUR
TI - Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm
T2 - IEICE TRANSACTIONS on Information
SP - 1171
EP - 1182
AU - Jungang GUAN
AU - Fengwei AN
AU - Xiangyu ZHANG
AU - Lei CHEN
AU - Hans Jürgen MATTAUSCH
PY - 2019
DO - 10.1587/transinf.2018EDP7279
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E102-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2019
AB - Efficient road-lane detection is expected to be achievable by application of the Hough transform (HT) which realizes high-accuracy straight-line extraction from images. The main challenge for HT-hardware implementation in actual applications is the trade-off optimization between accuracy maximization, power-dissipation reduction and real-time requirements. We report a HT-hardware architecture for road-lane detection with parallelized voting procedure, local maximum algorithm and FPGA-prototype implementation. Parallelization of the global design is realized on the basis of θ-value discretization in the Hough space. Four major hardware modules are developed for edge detection in the original video frames, computation of the characteristic edge-pixel values (ρ,θ) in Hough-space, voting procedure for each (ρ,θ) pair with parallel local-maximum-based peak voting-point extraction in Hough space to determine the detected straight lines. Implementation of a prototype system for real-time road-lane detection on a low-cost DE1 platform with a Cyclone II FPGA device was verified to be possible. An average detection speed of 135 frames/s for VGA (640x480)-frames was achieved at 50 MHz working frequency.
ER -