The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
휴대용 심전도계의 발전으로 심전도(ECG) 신호를 일상생활에서 기록할 수 있게 되었습니다. 딥러닝을 포함한 머신러닝 기술은 기존 방법보다 우수한 성능을 보이기 때문에 ECG 신호를 분석하기 위한 수많은 연구에서 사용되었습니다. 비정상적인 심전도를 어디서나 감지할 수 있으려면 이동식 심전도 분석 장치가 필요합니다. 이러한 모바일 장치는 실시간 성능과 낮은 전력 소비를 요구하지만, 딥러닝 기반 모델은 모바일 하드웨어에 구현하기에는 너무 많은 매개변수를 갖고 있고, 하드웨어의 양이 너무 많아 전력 소비를 많이 소모합니다. 저사양 FPGA에서 오토인코더를 사용하여 이상값 검출기를 구현하는 설계 흐름을 제안합니다. 오토인코더 학습에 사용되는 심전도 데이터 준비 시간을 단축하기 위해 비지도 학습 기법을 적용합니다. 또한 가중치 매개변수의 부피를 최소화하기 위해 가중치 희소성 기법을 적용하고 모든 매개변수를 고정 소수점 값으로 변환한다. 매개변수를 고정 소수점 값으로 변환하더라도 이상치 탐지 성능 저하가 0.83포인트에 불과하다는 것을 보여줍니다. 가중치 매개변수의 양을 줄임으로써 모든 매개변수를 온칩 메모리에 저장할 수 있습니다. 희소 행렬의 잘 알려진 데이터 구조인 CRS 형식에 따라 아키텍처를 설계하여 하드웨어 크기를 최소화하고 전력 소비를 줄입니다. 우리는 가중치 공유를 사용하여 가중치 매개변수 볼륨을 더욱 줄입니다. 가중치 공유를 사용하면 이상치 감지 성능을 유지하면서 메모리의 비트 폭을 60%까지 줄일 수 있었습니다. Digilent Inc.의 ZedBoard에 오토인코더를 구현하고 그 결과를 내장 장치용 ARM 모바일 CPU의 결과와 비교했습니다. 결과는 이상치 검출기의 FPGA 구현이 12배 더 빠르고 106배 더 에너지 효율적인 것으로 나타났습니다.
Naoto SOGA
Tokyo Institute of Technology
Shimpei SATO
Tokyo Institute of Technology
Hiroki NAKAHARA
Tokyo Institute of Technology
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Naoto SOGA, Shimpei SATO, Hiroki NAKAHARA, "Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder" in IEICE TRANSACTIONS on Information,
vol. E104-D, no. 8, pp. 1121-1129, August 2021, doi: 10.1587/transinf.2020LOP0011.
Abstract: Advancements in portable electrocardiographs have allowed electrocardiogram (ECG) signals to be recorded in everyday life. Machine-learning techniques, including deep learning, have been used in numerous studies to analyze ECG signals because they exhibit superior performance to conventional methods. A mobile ECG analysis device is needed so that abnormal ECG waves can be detected anywhere. Such mobile device requires a real-time performance and low power consumption, however, deep-learning based models often have too many parameters to implement on mobile hardware, its amount of hardware is too large and dissipates much power consumption. We propose a design flow to implement the outlier detector using an autoencoder on a low-end FPGA. To shorten the preparation time of ECG data used in training an autoencoder, an unsupervised learning technique is applied. Additionally, to minimize the volume of the weight parameters, a weight sparseness technique is applied, and all the parameters are converted into fixed-point values. We show that even if the parameters are reduced converted into fixed-point values, the outlier detection performance degradation is only 0.83 points. By reducing the volume of the weight parameters, all the parameters can be stored in on-chip memory. We design the architecture according to the CRS format, which is the well-known data structure of a sparse matrix, minimizing the hardware size and reducing the power consumption. We use weight sharing to further reduce the weight-parameter volumes. By using weight sharing, we could reduce the bit width of the memories by 60% while maintaining the outlier detection performance. We implemented the autoencoder on a Digilent Inc. ZedBoard and compared the results with those for the ARM mobile CPU for a built-in device. The results indicated that our FPGA implementation of the outlier detector was 12 times faster and 106 times more energy-efficient.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2020LOP0011/_p
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@ARTICLE{e104-d_8_1121,
author={Naoto SOGA, Shimpei SATO, Hiroki NAKAHARA, },
journal={IEICE TRANSACTIONS on Information},
title={Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder},
year={2021},
volume={E104-D},
number={8},
pages={1121-1129},
abstract={Advancements in portable electrocardiographs have allowed electrocardiogram (ECG) signals to be recorded in everyday life. Machine-learning techniques, including deep learning, have been used in numerous studies to analyze ECG signals because they exhibit superior performance to conventional methods. A mobile ECG analysis device is needed so that abnormal ECG waves can be detected anywhere. Such mobile device requires a real-time performance and low power consumption, however, deep-learning based models often have too many parameters to implement on mobile hardware, its amount of hardware is too large and dissipates much power consumption. We propose a design flow to implement the outlier detector using an autoencoder on a low-end FPGA. To shorten the preparation time of ECG data used in training an autoencoder, an unsupervised learning technique is applied. Additionally, to minimize the volume of the weight parameters, a weight sparseness technique is applied, and all the parameters are converted into fixed-point values. We show that even if the parameters are reduced converted into fixed-point values, the outlier detection performance degradation is only 0.83 points. By reducing the volume of the weight parameters, all the parameters can be stored in on-chip memory. We design the architecture according to the CRS format, which is the well-known data structure of a sparse matrix, minimizing the hardware size and reducing the power consumption. We use weight sharing to further reduce the weight-parameter volumes. By using weight sharing, we could reduce the bit width of the memories by 60% while maintaining the outlier detection performance. We implemented the autoencoder on a Digilent Inc. ZedBoard and compared the results with those for the ARM mobile CPU for a built-in device. The results indicated that our FPGA implementation of the outlier detector was 12 times faster and 106 times more energy-efficient.},
keywords={},
doi={10.1587/transinf.2020LOP0011},
ISSN={1745-1361},
month={August},}
부
TY - JOUR
TI - Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder
T2 - IEICE TRANSACTIONS on Information
SP - 1121
EP - 1129
AU - Naoto SOGA
AU - Shimpei SATO
AU - Hiroki NAKAHARA
PY - 2021
DO - 10.1587/transinf.2020LOP0011
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E104-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2021
AB - Advancements in portable electrocardiographs have allowed electrocardiogram (ECG) signals to be recorded in everyday life. Machine-learning techniques, including deep learning, have been used in numerous studies to analyze ECG signals because they exhibit superior performance to conventional methods. A mobile ECG analysis device is needed so that abnormal ECG waves can be detected anywhere. Such mobile device requires a real-time performance and low power consumption, however, deep-learning based models often have too many parameters to implement on mobile hardware, its amount of hardware is too large and dissipates much power consumption. We propose a design flow to implement the outlier detector using an autoencoder on a low-end FPGA. To shorten the preparation time of ECG data used in training an autoencoder, an unsupervised learning technique is applied. Additionally, to minimize the volume of the weight parameters, a weight sparseness technique is applied, and all the parameters are converted into fixed-point values. We show that even if the parameters are reduced converted into fixed-point values, the outlier detection performance degradation is only 0.83 points. By reducing the volume of the weight parameters, all the parameters can be stored in on-chip memory. We design the architecture according to the CRS format, which is the well-known data structure of a sparse matrix, minimizing the hardware size and reducing the power consumption. We use weight sharing to further reduce the weight-parameter volumes. By using weight sharing, we could reduce the bit width of the memories by 60% while maintaining the outlier detection performance. We implemented the autoencoder on a Digilent Inc. ZedBoard and compared the results with those for the ARM mobile CPU for a built-in device. The results indicated that our FPGA implementation of the outlier detector was 12 times faster and 106 times more energy-efficient.
ER -