The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
RISC-V는 2010년부터 개발된 RISC 기반 개방형 로열티 프리 명령어 세트 아키텍처로, FPGA의 비용 효율적인 소프트 프로세서에 사용할 수 있습니다. RISC-V의 기본 32비트 정수 명령어 세트는 RV32I로 정의되며 이는 운영 체제 환경을 지원하기에 충분하고 임베디드 시스템에 적합합니다. 본 논문에서는 32단계 파이프라이닝을 적용한 최적화된 RV7I 소프트 프로세서인 RVCoreP를 제안한다. 작동 주파수를 향상시키기 위해 세 가지 효과적인 방법이 프로세서에 적용됩니다. 이러한 방법에는 명령어 가져오기 단위 최적화, ALU 최적화 및 데이터 메모리 최적화가 있습니다. Verilog HDL에서 RVCoreP를 구현하고 Verilog 시뮬레이션과 실제 Xilinx Atrix-30.0 FPGA 보드를 사용하여 동작을 검증합니다. IPC(사이클당 명령), 작동 빈도, 하드웨어 리소스 활용도 및 프로세서 성능을 평가합니다. 평가 결과, RVCoreP는 일부 관련 연구에서 선정된 고성능 오픈소스 RV32I 프로세서인 VexRiscv에 비해 XNUMX%의 성능 향상을 달성한 것으로 나타났다.
Hiromu MIYAZAKI
Tokyo Institute of Technology
Takuto KANAMORI
Tokyo Institute of Technology
Md Ashraful ISLAM
Tokyo Institute of Technology
Kenji KISE
Tokyo Institute of Technology
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Hiromu MIYAZAKI, Takuto KANAMORI, Md Ashraful ISLAM, Kenji KISE, "RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining" in IEICE TRANSACTIONS on Information,
vol. E103-D, no. 12, pp. 2494-2503, December 2020, doi: 10.1587/transinf.2020PAP0015.
Abstract: RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2020PAP0015/_p
부
@ARTICLE{e103-d_12_2494,
author={Hiromu MIYAZAKI, Takuto KANAMORI, Md Ashraful ISLAM, Kenji KISE, },
journal={IEICE TRANSACTIONS on Information},
title={RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining},
year={2020},
volume={E103-D},
number={12},
pages={2494-2503},
abstract={RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.},
keywords={},
doi={10.1587/transinf.2020PAP0015},
ISSN={1745-1361},
month={December},}
부
TY - JOUR
TI - RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining
T2 - IEICE TRANSACTIONS on Information
SP - 2494
EP - 2503
AU - Hiromu MIYAZAKI
AU - Takuto KANAMORI
AU - Md Ashraful ISLAM
AU - Kenji KISE
PY - 2020
DO - 10.1587/transinf.2020PAP0015
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E103-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2020
AB - RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.
ER -