The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
현재 프로세서의 높은 에너지 소비로 인해 제한된 클록 주파수, 짧은 배터리 수명, 장치 신뢰성 감소 등 여러 가지 문제가 발생합니다. 따라서 프로세서의 에너지 소비를 줄이는 것이 중요합니다. 프로세서의 리소스 중에서 IQ(문제 대기열)는 에너지를 많이 소비하며, 그 중 대부분은 웨이크업 로직에 의해 소비됩니다. 웨이크업 로직 내에서 소스 피연산자 준비 상태를 확인하는 태그 비교는 상당한 양의 에너지를 소비합니다. 본 논문에서는 이중 단계 태그 비교라고 불리는 태그 비교를 위한 에너지 절감 방식을 제안합니다. 이 방식은 먼저 태그의 하위 비트를 비교한 다음 일치하는 경우에만 상위 비트를 비교합니다. 태그 비교의 에너지 소비는 비교된 총 비트 수에 대략 비례하기 때문에 이 수를 줄이면 에너지가 절약됩니다. 그러나 이러한 순차적 비교는 IQ의 지연을 증가시켜 클록 사이클 시간을 증가시킵니다. 발행 작업에 추가 주기를 할당하면 이를 방지할 수 있지만 결과적으로 IPC가 저하됩니다. IPC 저하를 방지하기 위해 성능에 부정적인 영향을 미칠 가능성이 있는 여러 가장 오래된 명령이 있는 IQ의 소수 항목을 태그 비교를 위한 단일 단계로 재구성합니다. SPEC2017 벤치마크 프로그램에 대한 평가 결과에 따르면 21단계 태그 비교는 웨이크업 로직에 의해 소비되는 에너지를 평균 15% 감소시키고(오버헤드를 포함할 경우 3.0%) 성능 저하를 XNUMX%만 달성하는 것으로 나타났습니다.
Yasutaka MATSUDA
Nagoya University
Ryota SHIOYA
the University of Tokyo
Hideki ANDO
Nagoya University
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부
Yasutaka MATSUDA, Ryota SHIOYA, Hideki ANDO, "Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison" in IEICE TRANSACTIONS on Information,
vol. E105-D, no. 2, pp. 320-332, February 2022, doi: 10.1587/transinf.2021EDP7174.
Abstract: The high energy consumption of current processors causes several problems, including a limited clock frequency, short battery lifetime, and reduced device reliability. It is therefore important to reduce the energy consumption of the processor. Among resources in a processor, the issue queue (IQ) is a large consumer of energy, much of which is consumed by the wakeup logic. Within the wakeup logic, the tag comparison that checks source operand readiness consumes a significant amount of energy. This paper proposes an energy reduction scheme for tag comparison, called double-stage tag comparison. This scheme first compares the lower bits of the tag and then, only if these match, compares the higher bits. Because the energy consumption of tag comparison is roughly proportional to the total number of bits compared, energy is saved by reducing this number. However, this sequential comparison increases the delay of the IQ, thereby increasing the clock cycle time. Although this can be avoided by allocating an extra cycle to the issue operation, this in turn degrades the IPC. To avoid IPC degradation, we reconfigure a small number of entries in the IQ, where several oldest instructions that are likely to have an adverse effect on performance reside, to a single stage for tag comparison. Our evaluation results for SPEC2017 benchmark programs show that the double-stage tag comparison achieves on average a 21% reduction in the energy consumed by the wakeup logic (15% when including the overhead) with only 3.0% performance degradation.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2021EDP7174/_p
부
@ARTICLE{e105-d_2_320,
author={Yasutaka MATSUDA, Ryota SHIOYA, Hideki ANDO, },
journal={IEICE TRANSACTIONS on Information},
title={Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison},
year={2022},
volume={E105-D},
number={2},
pages={320-332},
abstract={The high energy consumption of current processors causes several problems, including a limited clock frequency, short battery lifetime, and reduced device reliability. It is therefore important to reduce the energy consumption of the processor. Among resources in a processor, the issue queue (IQ) is a large consumer of energy, much of which is consumed by the wakeup logic. Within the wakeup logic, the tag comparison that checks source operand readiness consumes a significant amount of energy. This paper proposes an energy reduction scheme for tag comparison, called double-stage tag comparison. This scheme first compares the lower bits of the tag and then, only if these match, compares the higher bits. Because the energy consumption of tag comparison is roughly proportional to the total number of bits compared, energy is saved by reducing this number. However, this sequential comparison increases the delay of the IQ, thereby increasing the clock cycle time. Although this can be avoided by allocating an extra cycle to the issue operation, this in turn degrades the IPC. To avoid IPC degradation, we reconfigure a small number of entries in the IQ, where several oldest instructions that are likely to have an adverse effect on performance reside, to a single stage for tag comparison. Our evaluation results for SPEC2017 benchmark programs show that the double-stage tag comparison achieves on average a 21% reduction in the energy consumed by the wakeup logic (15% when including the overhead) with only 3.0% performance degradation.},
keywords={},
doi={10.1587/transinf.2021EDP7174},
ISSN={1745-1361},
month={February},}
부
TY - JOUR
TI - Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison
T2 - IEICE TRANSACTIONS on Information
SP - 320
EP - 332
AU - Yasutaka MATSUDA
AU - Ryota SHIOYA
AU - Hideki ANDO
PY - 2022
DO - 10.1587/transinf.2021EDP7174
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E105-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2022
AB - The high energy consumption of current processors causes several problems, including a limited clock frequency, short battery lifetime, and reduced device reliability. It is therefore important to reduce the energy consumption of the processor. Among resources in a processor, the issue queue (IQ) is a large consumer of energy, much of which is consumed by the wakeup logic. Within the wakeup logic, the tag comparison that checks source operand readiness consumes a significant amount of energy. This paper proposes an energy reduction scheme for tag comparison, called double-stage tag comparison. This scheme first compares the lower bits of the tag and then, only if these match, compares the higher bits. Because the energy consumption of tag comparison is roughly proportional to the total number of bits compared, energy is saved by reducing this number. However, this sequential comparison increases the delay of the IQ, thereby increasing the clock cycle time. Although this can be avoided by allocating an extra cycle to the issue operation, this in turn degrades the IPC. To avoid IPC degradation, we reconfigure a small number of entries in the IQ, where several oldest instructions that are likely to have an adverse effect on performance reside, to a single stage for tag comparison. Our evaluation results for SPEC2017 benchmark programs show that the double-stage tag comparison achieves on average a 21% reduction in the energy consumed by the wakeup logic (15% when including the overhead) with only 3.0% performance degradation.
ER -