The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
NoC(Network-on-Chip)는 확장 가능한 다중 코어 프로세서의 중요한 구성 요소입니다. 병렬 애플리케이션의 성능은 일반적으로 NoC의 대기 시간에 민감하므로 이를 줄이는 것이 기본 요구 사항입니다. 본 연구에서는 (압축 해제) 동작 지연을 숨기는 압축 라우터를 제안한다. 압축 라우터는 스위치 중재가 완료되기 전에 들어오는 패킷의 내용을 (해제)압축하여 대기 시간 패널티 없이 패킷 길이를 줄이고 네트워크 주입 및 제거 대기 시간을 줄입니다. 평가 결과, 압축 라우터는 병렬 응용 성능(공액 기울기(CG), 고속 푸리에 변환(FT), 정수 정렬(IS), 순회 판매원 문제(TSP))을 최대 33% 향상시켰고, NoC에서 압축률 63로 효과적인 네트워크 처리량. 비용은 라우터 면적이 증가하고 에너지 소비가 1.8mm 증가합니다.2 기존 가상채널 라우터에 비해 1.6배 향상된 성능을 제공합니다. 또 다른 발견은 압축 해제기를 네트워크 인터페이스로 오프로드하면 통신 대기 시간이 적당히 증가하는 대신 압축 라우터 영역이 57% 감소한다는 것입니다.
Naoya NIWA
Keio University
Yoshiya SHIKAMA
Keio University
Hideharu AMANO
Keio University
Michihiro KOIBUCHI
National Institute of Informatics,PRESTO JST
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Naoya NIWA, Yoshiya SHIKAMA, Hideharu AMANO, Michihiro KOIBUCHI, "A Compression Router for Low-Latency Network-on-Chip" in IEICE TRANSACTIONS on Information,
vol. E106-D, no. 2, pp. 170-180, February 2023, doi: 10.1587/transinf.2022EDP7080.
Abstract: Network-on-Chips (NoCs) are important components for scalable many-core processors. Because the performance of parallel applications is usually sensitive to the latency of NoCs, reducing it is a primary requirement. In this study, a compression router that hides the (de)compression-operation delay is proposed. The compression router (de)compresses the contents of the incoming packet before the switch arbitration is completed, thus shortening the packet length without latency penalty and reducing the network injection-and-ejection latency. Evaluation results show that the compression router improves up to 33% of the parallel application performance (conjugate gradients (CG), fast Fourier transform (FT), integer sort (IS), and traveling salesman problem (TSP)) and 63% of the effective network throughput by 1.8 compression ratio on NoC. The cost is an increase in router area and its energy consumption by 0.22mm2 and 1.6 times compared to the conventional virtual-channel router. Another finding is that off-loading the decompressor onto a network interface decreases the compression-router area by 57% at the expense of the moderate increase in communication latency.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2022EDP7080/_p
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@ARTICLE{e106-d_2_170,
author={Naoya NIWA, Yoshiya SHIKAMA, Hideharu AMANO, Michihiro KOIBUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={A Compression Router for Low-Latency Network-on-Chip},
year={2023},
volume={E106-D},
number={2},
pages={170-180},
abstract={Network-on-Chips (NoCs) are important components for scalable many-core processors. Because the performance of parallel applications is usually sensitive to the latency of NoCs, reducing it is a primary requirement. In this study, a compression router that hides the (de)compression-operation delay is proposed. The compression router (de)compresses the contents of the incoming packet before the switch arbitration is completed, thus shortening the packet length without latency penalty and reducing the network injection-and-ejection latency. Evaluation results show that the compression router improves up to 33% of the parallel application performance (conjugate gradients (CG), fast Fourier transform (FT), integer sort (IS), and traveling salesman problem (TSP)) and 63% of the effective network throughput by 1.8 compression ratio on NoC. The cost is an increase in router area and its energy consumption by 0.22mm2 and 1.6 times compared to the conventional virtual-channel router. Another finding is that off-loading the decompressor onto a network interface decreases the compression-router area by 57% at the expense of the moderate increase in communication latency.},
keywords={},
doi={10.1587/transinf.2022EDP7080},
ISSN={1745-1361},
month={February},}
부
TY - JOUR
TI - A Compression Router for Low-Latency Network-on-Chip
T2 - IEICE TRANSACTIONS on Information
SP - 170
EP - 180
AU - Naoya NIWA
AU - Yoshiya SHIKAMA
AU - Hideharu AMANO
AU - Michihiro KOIBUCHI
PY - 2023
DO - 10.1587/transinf.2022EDP7080
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E106-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2023
AB - Network-on-Chips (NoCs) are important components for scalable many-core processors. Because the performance of parallel applications is usually sensitive to the latency of NoCs, reducing it is a primary requirement. In this study, a compression router that hides the (de)compression-operation delay is proposed. The compression router (de)compresses the contents of the incoming packet before the switch arbitration is completed, thus shortening the packet length without latency penalty and reducing the network injection-and-ejection latency. Evaluation results show that the compression router improves up to 33% of the parallel application performance (conjugate gradients (CG), fast Fourier transform (FT), integer sort (IS), and traveling salesman problem (TSP)) and 63% of the effective network throughput by 1.8 compression ratio on NoC. The cost is an increase in router area and its energy consumption by 0.22mm2 and 1.6 times compared to the conventional virtual-channel router. Another finding is that off-loading the decompressor onto a network interface decreases the compression-router area by 57% at the expense of the moderate increase in communication latency.
ER -