The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
스캔 테스트 중 높은 전력 소비로 인해 특히 저전력 회로의 경우 과도한 수율 손실이 발생하는 경우가 많습니다. 한 가지 주요 이유는 변속 모드에서 발생하는 IR 드롭으로 인해 테스트 데이터가 손상될 수 있다는 것입니다. 이 문제를 해결하기 위한 일반적인 접근 방식은 여러 스캔 체인이 형성되고 한 번에 하나의 스캔 체인 그룹만 이동하는 부분 이동입니다. 그러나 기존의 부분 변속 기반 방법은 두 가지 주요 문제를 안고 있습니다. (1) IR 강하 추정이 각 변속 주기에 대해 수행하기에는 충분히 정확하지 않거나 계산 비용이 너무 많이 듭니다. (2) 따라서 모든 변속 사이클에 부분 변속이 적용되어 테스트 시간이 길어집니다. 이 백서에서는 다음 기능을 갖춘 새로운 IR 드롭 인식 스캔 이동 방법으로 이러한 두 가지 문제를 해결합니다. (1) GPU 가속 동적 전력 시뮬레이터에서 지원되는 사이클 기반 IR 드롭 추정(CIDE)으로 과도한 전류가 흐르는 잠재적인 시프트 사이클을 신속하게 찾습니다. 피크 IR 강하; (2) 테스트 시간에 미치는 영향을 줄이기 위해 고려되는 각 교대 사이클을 대상으로 하는 스캔 체인 그룹화를 생성하는 스캔 교대 스케줄링 방법. ITC'99 벤치마크 회로에 대한 실험은 다음을 보여줍니다. (1) CIDE는 계산적으로 실행 가능합니다. (2) 제안된 스캔 시프트 일정은 최대 47%의 글로벌 피크 IR 강하 감소를 달성할 수 있습니다. 기존의 일반적인 방법에 비해 스케줄링 효율성이 평균 58.4% 높아 테스트 시간이 단축됩니다.
Shiling SHI
Kyushu Institute of Technology
Stefan HOLST
Kyushu Institute of Technology
Xiaoqing WEN
Kyushu Institute of Technology
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부
Shiling SHI, Stefan HOLST, Xiaoqing WEN, "GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting" in IEICE TRANSACTIONS on Information,
vol. E106-D, no. 10, pp. 1694-1704, October 2023, doi: 10.1587/transinf.2023EDP7011.
Abstract: High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2023EDP7011/_p
부
@ARTICLE{e106-d_10_1694,
author={Shiling SHI, Stefan HOLST, Xiaoqing WEN, },
journal={IEICE TRANSACTIONS on Information},
title={GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting},
year={2023},
volume={E106-D},
number={10},
pages={1694-1704},
abstract={High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.},
keywords={},
doi={10.1587/transinf.2023EDP7011},
ISSN={1745-1361},
month={October},}
부
TY - JOUR
TI - GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting
T2 - IEICE TRANSACTIONS on Information
SP - 1694
EP - 1704
AU - Shiling SHI
AU - Stefan HOLST
AU - Xiaoqing WEN
PY - 2023
DO - 10.1587/transinf.2023EDP7011
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E106-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2023
AB - High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.
ER -