The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
라인 분기 파티셔닝을 기반으로 하는 Xilinx FPGA(Field Programmable Gate Array)의 새로운 애플리케이션 종속 상호 연결 테스트 방식이 제시됩니다. FPGA의 AC(애플리케이션 구성)에 있는 상호 연결의 대상 라인 분기는 여러 하위 세트로 분할되므로 여러 테스트 구성(TC)에서 호환 가능한 CLB(구성 가능 논리 블록) 구성을 사용하여 테스트할 수 있습니다. 실험 결과에 따르면 ISCAS89 및 ITC99 벤치마크의 경우 이 체계는 99개 TC 미만에서 11%보다 높은 고착 오류 범위를 얻을 수 있습니다.
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Teng LIN, Jianhua FENG, Dunshan YU, "Application-Dependent Interconnect Testing of Xilinx FPGAs Based on Line Branches Partitioning" in IEICE TRANSACTIONS on Information,
vol. E92-D, no. 5, pp. 1197-1199, May 2009, doi: 10.1587/transinf.E92.D.1197.
Abstract: A novel application-dependent interconnect testing scheme of Xilinx Field Programmable Gate Arrays (FPGAs) based on line branches partitioning is presented. The targeted line branches of the interconnects in FPGAs' Application Configurations (ACs) are partitioned into multiple subsets, so that they can be tested with compatible Configurable Logic Blocks (CLBs) configurations in multiple Test Configurations (TCs). Experimental results show that for ISCAS89 and ITC99 benchmarks, this scheme can obtain a stuck-at fault coverage higher than 99% in less than 11 TCs.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.1197/_p
부
@ARTICLE{e92-d_5_1197,
author={Teng LIN, Jianhua FENG, Dunshan YU, },
journal={IEICE TRANSACTIONS on Information},
title={Application-Dependent Interconnect Testing of Xilinx FPGAs Based on Line Branches Partitioning},
year={2009},
volume={E92-D},
number={5},
pages={1197-1199},
abstract={A novel application-dependent interconnect testing scheme of Xilinx Field Programmable Gate Arrays (FPGAs) based on line branches partitioning is presented. The targeted line branches of the interconnects in FPGAs' Application Configurations (ACs) are partitioned into multiple subsets, so that they can be tested with compatible Configurable Logic Blocks (CLBs) configurations in multiple Test Configurations (TCs). Experimental results show that for ISCAS89 and ITC99 benchmarks, this scheme can obtain a stuck-at fault coverage higher than 99% in less than 11 TCs.},
keywords={},
doi={10.1587/transinf.E92.D.1197},
ISSN={1745-1361},
month={May},}
부
TY - JOUR
TI - Application-Dependent Interconnect Testing of Xilinx FPGAs Based on Line Branches Partitioning
T2 - IEICE TRANSACTIONS on Information
SP - 1197
EP - 1199
AU - Teng LIN
AU - Jianhua FENG
AU - Dunshan YU
PY - 2009
DO - 10.1587/transinf.E92.D.1197
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2009
AB - A novel application-dependent interconnect testing scheme of Xilinx Field Programmable Gate Arrays (FPGAs) based on line branches partitioning is presented. The targeted line branches of the interconnects in FPGAs' Application Configurations (ACs) are partitioned into multiple subsets, so that they can be tested with compatible Configurable Logic Blocks (CLBs) configurations in multiple Test Configurations (TCs). Experimental results show that for ISCAS89 and ITC99 benchmarks, this scheme can obtain a stuck-at fault coverage higher than 99% in less than 11 TCs.
ER -