The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 다양한 종류의 테스트 알고리즘을 지원할 수 있는 마이크로코드 기반 PMBIST(Programmable Memory BIST) 아키텍처를 제안한다. 제안된 비선형 PMBIST(NPMBIST)는 March 알고리즘뿐만 아니라 Walking, Galloping 등의 비선형 알고리즘을 사용하여 높은 유연성과 높은 장애 커버리지를 보장합니다. 이 NPMBIST는 최적화된 명령어에 의해 최소 비트로 알고리즘을 구현할 수 있으므로 최적화된 하드웨어 오버헤드를 갖습니다. 마지막으로 다중 루프 지원으로 다양하고 복잡한 알고리즘을 실행할 수 있습니다.
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Youngkyu PARK, Jaeseok PARK, Taewoo HAN, Sungho KANG, "An Effective Programmable Memory BIST for Embedded Memory" in IEICE TRANSACTIONS on Information,
vol. E92-D, no. 12, pp. 2508-2511, December 2009, doi: 10.1587/transinf.E92.D.2508.
Abstract: This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST) guarantees high flexibility and high fault coverage using not only March algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be implemented with the minimum bits by the optimized instructions. Finally, various and complex algorithms can be run thanks to its support of multi-loop.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.2508/_p
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@ARTICLE{e92-d_12_2508,
author={Youngkyu PARK, Jaeseok PARK, Taewoo HAN, Sungho KANG, },
journal={IEICE TRANSACTIONS on Information},
title={An Effective Programmable Memory BIST for Embedded Memory},
year={2009},
volume={E92-D},
number={12},
pages={2508-2511},
abstract={This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST) guarantees high flexibility and high fault coverage using not only March algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be implemented with the minimum bits by the optimized instructions. Finally, various and complex algorithms can be run thanks to its support of multi-loop.},
keywords={},
doi={10.1587/transinf.E92.D.2508},
ISSN={1745-1361},
month={December},}
부
TY - JOUR
TI - An Effective Programmable Memory BIST for Embedded Memory
T2 - IEICE TRANSACTIONS on Information
SP - 2508
EP - 2511
AU - Youngkyu PARK
AU - Jaeseok PARK
AU - Taewoo HAN
AU - Sungho KANG
PY - 2009
DO - 10.1587/transinf.E92.D.2508
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2009
AB - This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST) guarantees high flexibility and high fault coverage using not only March algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be implemented with the minimum bits by the optimized instructions. Finally, various and complex algorithms can be run thanks to its support of multi-loop.
ER -