The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 효율적인 테스트 압축을 제공하는 방법을 제안한다. 제안된 방법은 두 가지 패턴 테스트를 용이하게 하는 스캔 설계를 통해 강력한 테스트 가능한 경로 지연 오류 테스트를 위한 것입니다. 제안하는 방법에서는 통계 코딩을 이용하여 테스트 압축 전 테스트 데이터를 인터리브한다. 또한 본 논문에서는 제안된 방법을 사용하여 11패턴 테스트를 위한 테스트 아키텍처를 제시합니다. 제안된 방법은 압축률, 테스트 적용 시간, 면적 오버헤드 등 여러 관점에서 실험적으로 평가되었습니다. ISCAS20 벤치마크 회로 89개 중 XNUMX개에 대한 강력한 테스트 가능한 경로 지연 오류 테스트를 위해 제안된 방법은 Huffman 코딩, 실행 길이 코딩, Golomb 코딩, FDR(Frequency-Directed Run-Length) 코딩과 같은 기존 방법보다 더 나은 압축률을 제공합니다. 및 가변 길이 입력 허프만 코딩(VIHC).
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Kazuteru NAMBA, Hideo ITO, "Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding" in IEICE TRANSACTIONS on Information,
vol. E92-D, no. 2, pp. 269-282, February 2009, doi: 10.1587/transinf.E92.D.269.
Abstract: This paper proposes a method providing efficient test compression. The proposed method is for robust testable path delay fault testing with scan design facilitating two-pattern testing. In the proposed method, test data are interleaved before test compression using statistical coding. This paper also presents test architecture for two-pattern testing using the proposed method. The proposed method is experimentally evaluated from several viewpoints such as compression rates, test application time and area overhead. For robust testable path delay fault testing on 11 out of 20 ISCAS89 benchmark circuits, the proposed method provides better compression rates than the existing methods such as Huffman coding, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC).
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.269/_p
부
@ARTICLE{e92-d_2_269,
author={Kazuteru NAMBA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding},
year={2009},
volume={E92-D},
number={2},
pages={269-282},
abstract={This paper proposes a method providing efficient test compression. The proposed method is for robust testable path delay fault testing with scan design facilitating two-pattern testing. In the proposed method, test data are interleaved before test compression using statistical coding. This paper also presents test architecture for two-pattern testing using the proposed method. The proposed method is experimentally evaluated from several viewpoints such as compression rates, test application time and area overhead. For robust testable path delay fault testing on 11 out of 20 ISCAS89 benchmark circuits, the proposed method provides better compression rates than the existing methods such as Huffman coding, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC).},
keywords={},
doi={10.1587/transinf.E92.D.269},
ISSN={1745-1361},
month={February},}
부
TY - JOUR
TI - Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
T2 - IEICE TRANSACTIONS on Information
SP - 269
EP - 282
AU - Kazuteru NAMBA
AU - Hideo ITO
PY - 2009
DO - 10.1587/transinf.E92.D.269
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2009
AB - This paper proposes a method providing efficient test compression. The proposed method is for robust testable path delay fault testing with scan design facilitating two-pattern testing. In the proposed method, test data are interleaved before test compression using statistical coding. This paper also presents test architecture for two-pattern testing using the proposed method. The proposed method is experimentally evaluated from several viewpoints such as compression rates, test application time and area overhead. For robust testable path delay fault testing on 11 out of 20 ISCAS89 benchmark circuits, the proposed method provides better compression rates than the existing methods such as Huffman coding, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC).
ER -