The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
컴퓨터 메모리 시스템 성능 향상을 위한 리소스 무기고에서 지난 몇 년간 예측 변수의 역할이 점점 더 커지고 있습니다. 캐시나 주 메모리에 액세스할 때 대기 시간을 억제할 수 있습니다. 논문 [1]에서는 라이브 타임, 데드 타임, 액세스 간격으로 정의된 캐시 메모리 액세스의 시간 매개변수가 데이터 프리페칭 예측에 어떻게 사용될 수 있는지 보여줍니다. 본 논문에서는 다양한 개선을 통해 DRAM 메모리 행의 열기/닫기 제어에 아날로그 기술을 적용하는 타당성을 조사합니다. 여기에 설명된 결과는 타당성을 확인하고 열려 있는 DRAM 행을 닫을 뿐만 아니라 다음 열이 열리는 행을 예측하는 예측기를 갖춘 DRAM 컨트롤러를 제안할 수 있게 해줍니다.
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부
Vladimir V. STANKOVIC, Nebojsa Z. MILENKOVIC, "DRAM Controller with a Complete Predictor" in IEICE TRANSACTIONS on Information,
vol. E92-D, no. 4, pp. 584-593, April 2009, doi: 10.1587/transinf.E92.D.584.
Abstract: In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.584/_p
부
@ARTICLE{e92-d_4_584,
author={Vladimir V. STANKOVIC, Nebojsa Z. MILENKOVIC, },
journal={IEICE TRANSACTIONS on Information},
title={DRAM Controller with a Complete Predictor},
year={2009},
volume={E92-D},
number={4},
pages={584-593},
abstract={In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.},
keywords={},
doi={10.1587/transinf.E92.D.584},
ISSN={1745-1361},
month={April},}
부
TY - JOUR
TI - DRAM Controller with a Complete Predictor
T2 - IEICE TRANSACTIONS on Information
SP - 584
EP - 593
AU - Vladimir V. STANKOVIC
AU - Nebojsa Z. MILENKOVIC
PY - 2009
DO - 10.1587/transinf.E92.D.584
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2009
AB - In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.
ER -