The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 알고리즘 설명부터 게이트 수준 구현에 이르기까지 다양한 설계 단계에서 데이터 경로 지향 하드웨어 설계의 동등성 검사를 목적으로 Horner Expansion Diagram(HED)[1]이라는 표준 결정 다이어그램을 기반으로 하는 통합 프레임워크를 소개합니다. . HED는 모듈로 동등성을 갖춘 다항식의 관점에서 알고리즘 사양을 표현하고 조작할 수 있을 뿐만 아니라 게이트 수준 구현의 비트 수준 가산기(BLA) 설명도 표현할 수 있습니다. 우리의 HED는 다음 형식의 정수 링에 대한 모듈러 산술 연산을 지원할 수 있습니다. Z2n. 제안된 기법은 산업 벤치마크의 동등성 검사에 성공적으로 적용되었습니다. 다양한 애플리케이션에 대한 실험 결과는 기존 비트 수준 및 단어 수준 동등성 검사 기술에 비해 상당한 이점을 보여주었습니다.
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부
Bijan ALIZADEH, Masahiro FUJITA, "A Unified Framework for Equivalence Verification of Datapath Oriented Applications" in IEICE TRANSACTIONS on Information,
vol. E92-D, no. 5, pp. 985-994, May 2009, doi: 10.1587/transinf.E92.D.985.
Abstract: In this paper, we introduce a unified framework based on a canonical decision diagram called Horner Expansion Diagram (HED) [1] for the purpose of equivalence checking of datapath oriented hardware designs in various design stages from an algorithmic description to the gate-level implementation. The HED is not only able to represent and manipulate algorithmic specifications in terms of polynomial expressions with modulo equivalence but also express bit level adder (BLA) description of gate-level implementations. Our HED can support modular arithmetic operations over integer rings of the form Z2n. The proposed techniques have successfully been applied to equivalence checking on industrial benchmarks. The experimental results on different applications have shown the significant advantages over existing bit-level and also word-level equivalence checking techniques.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.985/_p
부
@ARTICLE{e92-d_5_985,
author={Bijan ALIZADEH, Masahiro FUJITA, },
journal={IEICE TRANSACTIONS on Information},
title={A Unified Framework for Equivalence Verification of Datapath Oriented Applications},
year={2009},
volume={E92-D},
number={5},
pages={985-994},
abstract={In this paper, we introduce a unified framework based on a canonical decision diagram called Horner Expansion Diagram (HED) [1] for the purpose of equivalence checking of datapath oriented hardware designs in various design stages from an algorithmic description to the gate-level implementation. The HED is not only able to represent and manipulate algorithmic specifications in terms of polynomial expressions with modulo equivalence but also express bit level adder (BLA) description of gate-level implementations. Our HED can support modular arithmetic operations over integer rings of the form Z2n. The proposed techniques have successfully been applied to equivalence checking on industrial benchmarks. The experimental results on different applications have shown the significant advantages over existing bit-level and also word-level equivalence checking techniques.},
keywords={},
doi={10.1587/transinf.E92.D.985},
ISSN={1745-1361},
month={May},}
부
TY - JOUR
TI - A Unified Framework for Equivalence Verification of Datapath Oriented Applications
T2 - IEICE TRANSACTIONS on Information
SP - 985
EP - 994
AU - Bijan ALIZADEH
AU - Masahiro FUJITA
PY - 2009
DO - 10.1587/transinf.E92.D.985
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2009
AB - In this paper, we introduce a unified framework based on a canonical decision diagram called Horner Expansion Diagram (HED) [1] for the purpose of equivalence checking of datapath oriented hardware designs in various design stages from an algorithmic description to the gate-level implementation. The HED is not only able to represent and manipulate algorithmic specifications in terms of polynomial expressions with modulo equivalence but also express bit level adder (BLA) description of gate-level implementations. Our HED can support modular arithmetic operations over integer rings of the form Z2n. The proposed techniques have successfully been applied to equivalence checking on industrial benchmarks. The experimental results on different applications have shown the significant advantages over existing bit-level and also word-level equivalence checking techniques.
ER -