The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
회로의 잘못된 경로에 대한 정보는 설계 및 테스트에 유용합니다. 이 정보를 활용하면 회로 면적을 줄이고 회로의 논리 합성, 테스트 생성 및 테스트 적용에 필요한 시간을 줄일 수 있을 뿐만 아니라 과잉 테스트를 완화하는 데에도 기여할 수 있습니다. 게이트 수준에서 잘못된 경로를 식별하는 것은 어렵기 때문에 상위 수준 설계 정보를 사용하는 여러 가지 방법이 제안되었습니다. 이러한 방법은 RTL(레지스터 전송 수준)과 게이트 수준의 경로 간 대응이 설정될 수 있는 경우에만 효과적입니다. 지금까지는 논리 합성에 제한을 두는 것이 일치성을 확립하는 유일한 방법이었습니다. 그러나 산업 디자인에는 실용적이지 않습니다. 본 논문에서는 이러한 특정 논리 합성 없이 RTL 거짓 경로를 해당 게이트 레벨 경로에 매핑하는 방법을 제안합니다. 해당 게이트 수준 경로가 거짓임을 보장합니다. 실험 결과는 우리의 경로 매핑 방법이 RTL 잘못된 경로와 많은 게이트 수준 잘못된 경로의 대응을 설정할 수 있음을 보여줍니다.
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부
Hiroshi IWATA, Satoshi OHTAKE, Hideo FUJIWARA, "A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 7, pp. 1857-1865, July 2010, doi: 10.1587/transinf.E93.D.1857.
Abstract: Information on false paths in a circuit is useful for design and testing. The use of this information may contribute not only to reducing circuit area, the time required for logic synthesis, test generation and test application of the circuit, but also to alleviating over-testing. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, giving restriction on logic synthesis is the only way to establish the correspondence. However, it is not practical for industrial designs. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis; it guarantees that the corresponding gate level paths are false. Experimental results show that our path mapping method can establish the correspondences of RTL false paths and many gate level false paths.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.1857/_p
부
@ARTICLE{e93-d_7_1857,
author={Hiroshi IWATA, Satoshi OHTAKE, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification},
year={2010},
volume={E93-D},
number={7},
pages={1857-1865},
abstract={Information on false paths in a circuit is useful for design and testing. The use of this information may contribute not only to reducing circuit area, the time required for logic synthesis, test generation and test application of the circuit, but also to alleviating over-testing. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, giving restriction on logic synthesis is the only way to establish the correspondence. However, it is not practical for industrial designs. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis; it guarantees that the corresponding gate level paths are false. Experimental results show that our path mapping method can establish the correspondences of RTL false paths and many gate level false paths.},
keywords={},
doi={10.1587/transinf.E93.D.1857},
ISSN={1745-1361},
month={July},}
부
TY - JOUR
TI - A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification
T2 - IEICE TRANSACTIONS on Information
SP - 1857
EP - 1865
AU - Hiroshi IWATA
AU - Satoshi OHTAKE
AU - Hideo FUJIWARA
PY - 2010
DO - 10.1587/transinf.E93.D.1857
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2010
AB - Information on false paths in a circuit is useful for design and testing. The use of this information may contribute not only to reducing circuit area, the time required for logic synthesis, test generation and test application of the circuit, but also to alleviating over-testing. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, giving restriction on logic synthesis is the only way to establish the correspondence. However, it is not practical for industrial designs. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis; it guarantees that the corresponding gate level paths are false. Experimental results show that our path mapping method can establish the correspondences of RTL false paths and many gate level false paths.
ER -