The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
속도 스캔 테스트는 과도한 발사 스위칭 활동으로 인한 전원 공급 장치 소음으로 인한 수율 손실 위험에 취약합니다. 본 논문에서는 테스트 자극이 시작될 때 스위칭 활동을 줄이기 위한 새로운 1단계 방식, 즉 CTX(Clock-Gating-Based Test Relaxation and X-Filling)를 제안합니다. 테스트 완화 및 X-필링은 (1) Stage-2(Clock-Disabling)에서 클록 게이팅 회로의 해당 클록 제어 신호를 비활성화하여 가능한 한 많은 FF를 비활성화하고 (2) 입력과 출력을 균등화하기 위해 수행됩니다. 가능한 한 많은 남아 있는 활성 FF의 XNUMX단계 값(FF-Silencing). CTX는 실행 스위칭 활동을 효과적으로 줄여 테스트 데이터 볼륨, 오류 적용 범위, 성능 또는 회로 설계에 영향을 주지 않고 소수의 상관 없음(X) 비트만 존재하는 경우에도(테스트 압축에서와 같이) 손실 위험을 발생시킵니다. .
Kohei MIYASE
Xiaoqing WEN
Hiroshi FURUKAWA
Yuta YAMATO
Seiji KAJIHARA
Patrick GIRARD
Laung-Terng WANG
Mohammad TEHRANIPOOR
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Kohei MIYASE, Xiaoqing WEN, Hiroshi FURUKAWA, Yuta YAMATO, Seiji KAJIHARA, Patrick GIRARD, Laung-Terng WANG, Mohammad TEHRANIPOOR, "High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 1, pp. 2-9, January 2010, doi: 10.1587/transinf.E93.D.2.
Abstract: At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2/_p
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@ARTICLE{e93-d_1_2,
author={Kohei MIYASE, Xiaoqing WEN, Hiroshi FURUKAWA, Yuta YAMATO, Seiji KAJIHARA, Patrick GIRARD, Laung-Terng WANG, Mohammad TEHRANIPOOR, },
journal={IEICE TRANSACTIONS on Information},
title={High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme},
year={2010},
volume={E93-D},
number={1},
pages={2-9},
abstract={At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.},
keywords={},
doi={10.1587/transinf.E93.D.2},
ISSN={1745-1361},
month={January},}
부
TY - JOUR
TI - High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme
T2 - IEICE TRANSACTIONS on Information
SP - 2
EP - 9
AU - Kohei MIYASE
AU - Xiaoqing WEN
AU - Hiroshi FURUKAWA
AU - Yuta YAMATO
AU - Seiji KAJIHARA
AU - Patrick GIRARD
AU - Laung-Terng WANG
AU - Mohammad TEHRANIPOOR
PY - 2010
DO - 10.1587/transinf.E93.D.2
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2010
AB - At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.
ER -