The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 먼저 전력 소모와 프로그래밍 가능성에 초점을 맞춰 VLSI 설계 동향을 검토합니다. 그런 다음 논리 기능을 표현하고 평가하는 데 QDD(분기 결정 다이어그램)의 이점을 보여줍니다. 즉, QDD를 사용하여 고속 구현을 제공하는 QDD 머신을 구현하는 방법을 보여줍니다. QDD 머신을 BDD(Binary Decision Diagram) 머신과 비교한 결과, QDD를 선택한 경우 1.28~2.02배의 속도 향상을 보여줍니다. 1주소와 2주소 BDD 머신, 3주소와 4주소 QDD 머신을 고려하여 명령어 수를 최소화하는 방법을 보여줍니다.
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Tsutomu SASAO, Hiroki NAKAHARA, Munehiro MATSUURA, Yoshifumi KAWAMURA, Jon T. BUTLER, "A Quaternary Decision Diagram Machine: Optimization of Its Code" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2026-2035, August 2010, doi: 10.1587/transinf.E93.D.2026.
Abstract: This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2026/_p
부
@ARTICLE{e93-d_8_2026,
author={Tsutomu SASAO, Hiroki NAKAHARA, Munehiro MATSUURA, Yoshifumi KAWAMURA, Jon T. BUTLER, },
journal={IEICE TRANSACTIONS on Information},
title={A Quaternary Decision Diagram Machine: Optimization of Its Code},
year={2010},
volume={E93-D},
number={8},
pages={2026-2035},
abstract={This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.},
keywords={},
doi={10.1587/transinf.E93.D.2026},
ISSN={1745-1361},
month={August},}
부
TY - JOUR
TI - A Quaternary Decision Diagram Machine: Optimization of Its Code
T2 - IEICE TRANSACTIONS on Information
SP - 2026
EP - 2035
AU - Tsutomu SASAO
AU - Hiroki NAKAHARA
AU - Munehiro MATSUURA
AU - Yoshifumi KAWAMURA
AU - Jon T. BUTLER
PY - 2010
DO - 10.1587/transinf.E93.D.2026
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2010
AB - This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.
ER -