The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이진 논리 회로에 대한 지연 모델이 제안되었으며 수학적 특성이 명확해졌습니다. Kleene의 삼항 논리는 이진 논리 회로의 과도 동작을 표현하는 가장 간단한 지연 모델 중 하나입니다. Goto는 1948년에 처음으로 Kleene의 삼항 논리를 이진 논리 회로의 위험 감지에 적용했습니다. Kleene의 삼항 논리 외에도 이진 논리 회로의 지연 모델, Lewis의 5가 논리 등이 많이 있습니다. 한편, 최근에는 다치 논리 회로가 재생되고 있습니다. 디지털 회로를 구현하는 데 중요한 역할을 합니다. 예를 들어 칩 크기를 획기적으로 줄일 수 있기 때문입니다. 다중 값 논리 회로가 더욱 중요해짐에도 불구하고 다중 값 논리 회로의 지연 모델에 대한 논의는 거의 없습니다. 그리고 본 논문에서는 Min, Max, Literal 연산으로 구성된 다중값 논리회로의 지연 모델을 소개한다. 그런 다음 지연 모델의 수학적 속성 중 일부를 보여줍니다.
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Noboru TAKAGI, "A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2040-2047, August 2010, doi: 10.1587/transinf.E93.D.2040.
Abstract: Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2040/_p
부
@ARTICLE{e93-d_8_2040,
author={Noboru TAKAGI, },
journal={IEICE TRANSACTIONS on Information},
title={A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations},
year={2010},
volume={E93-D},
number={8},
pages={2040-2047},
abstract={Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.},
keywords={},
doi={10.1587/transinf.E93.D.2040},
ISSN={1745-1361},
month={August},}
부
TY - JOUR
TI - A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations
T2 - IEICE TRANSACTIONS on Information
SP - 2040
EP - 2047
AU - Noboru TAKAGI
PY - 2010
DO - 10.1587/transinf.E93.D.2040
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2010
AB - Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.
ER -