The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 논문에서는 여러 Si 기반 금속 산화막 반도체 전계 효과 트랜지스터(MOS)와 SiGe 회로로 구성된 3피크 음차동 저항(NDR) 회로를 사용하는 새로운 다중 값 논리(MVL) 설계를 보여줍니다. 이종접합 바이폴라 트랜지스터(HBT) 기반 장치. 특히 이 3피크 NDR 회로는 2개의 스위치 제어 전류 소스에 의해 바이어스됩니다. 공진 터널링 다이오드(RTD)로 만들어진 기존 MVL 회로와 비교할 때 이 다중 피크 MOS-HBT-NDR 회로는 두 가지 주요 장점을 가지고 있습니다. 하나는 이 회로의 제작이 분자빔 에피택시 시스템 없이도 표준 BiCMOS 공정으로 완벽하게 구현될 수 있다는 것입니다. 또 다른 점은 RTD 기반 MVL 설계보다 더 많은 논리 상태를 얻을 수 있다는 것입니다. 측정 시 두 개의 전류원을 순서대로 켜고 끄는 순차적 제어에 따라 출력에서 8개의 논리 상태를 얻을 수 있습니다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Kwang-Jow GAN, Dong-Shong LIANG, Yan-Wun CHEN, "Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2068-2072, August 2010, doi: 10.1587/transinf.E93.D.2068.
Abstract: The paper demonstrates a novel multiple-valued logic (MVL) design using a three-peak negative differential resistance (NDR) circuit, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices. Specifically, this three-peak NDR circuit is biased by two switch-controlled current sources. Compared to the traditional MVL circuit made of resonant tunneling diode (RTD), this multiple-peak MOS-HBT-NDR circuit has two major advantages. One is that the fabrication of this circuit can be fully implemented by the standard BiCMOS process without the need for molecular-beam epitaxy system. Another is that we can obtain more logic states than the RTD-based MVL design. In measuring, we can obtain eight logic states at the output according to a sequent control of two current sources on and off in order.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2068/_p
부
@ARTICLE{e93-d_8_2068,
author={Kwang-Jow GAN, Dong-Shong LIANG, Yan-Wun CHEN, },
journal={IEICE TRANSACTIONS on Information},
title={Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources},
year={2010},
volume={E93-D},
number={8},
pages={2068-2072},
abstract={The paper demonstrates a novel multiple-valued logic (MVL) design using a three-peak negative differential resistance (NDR) circuit, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices. Specifically, this three-peak NDR circuit is biased by two switch-controlled current sources. Compared to the traditional MVL circuit made of resonant tunneling diode (RTD), this multiple-peak MOS-HBT-NDR circuit has two major advantages. One is that the fabrication of this circuit can be fully implemented by the standard BiCMOS process without the need for molecular-beam epitaxy system. Another is that we can obtain more logic states than the RTD-based MVL design. In measuring, we can obtain eight logic states at the output according to a sequent control of two current sources on and off in order.},
keywords={},
doi={10.1587/transinf.E93.D.2068},
ISSN={1745-1361},
month={August},}
부
TY - JOUR
TI - Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources
T2 - IEICE TRANSACTIONS on Information
SP - 2068
EP - 2072
AU - Kwang-Jow GAN
AU - Dong-Shong LIANG
AU - Yan-Wun CHEN
PY - 2010
DO - 10.1587/transinf.E93.D.2068
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2010
AB - The paper demonstrates a novel multiple-valued logic (MVL) design using a three-peak negative differential resistance (NDR) circuit, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices. Specifically, this three-peak NDR circuit is biased by two switch-controlled current sources. Compared to the traditional MVL circuit made of resonant tunneling diode (RTD), this multiple-peak MOS-HBT-NDR circuit has two major advantages. One is that the fabrication of this circuit can be fully implemented by the standard BiCMOS process without the need for molecular-beam epitaxy system. Another is that we can obtain more logic states than the RTD-based MVL design. In measuring, we can obtain eight logic states at the output according to a sequent control of two current sources on and off in order.
ER -