The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
버스 기반 SoC(시스템 온 칩) 설계는 SoC 설계 시간을 단축하기 위한 주요 통합 방법론이 되었습니다. 주요 과제는 온칩 버스 프로토콜을 효율적으로 검증하는 방법입니다. 기존의 시뮬레이션 기반 버스 프로토콜 모니터는 버스 신호가 버스 프로토콜을 준수하는지 여부를 확인할 수 있습니다. FPGA 레벨이나 칩 레벨과 같은 효율적인 버스 프로토콜 검증 환경이 여전히 부족합니다. 부족함을 극복하기 위해 우리는 AHB 버스 신호 동작을 확인하기 위한 73개의 관련 AHB 온칩 버스 프로토콜 규칙과 두 개의 해당 검증 메커니즘인 오류 참조 테이블을 포함하는 규칙 기반 합성 가능한 AMBA AHB 온칩 버스 프로토콜 검사기를 제안합니다. ERT) 및 창 추적 버퍼를 사용하여 확인 시간을 단축합니다.
AMBA, 디버깅, SoC(시스템 온 칩), 프로토콜 검사기, 확인
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부
Liang-Bi CHEN, Jiun-Cheng JU, Chien-Chou WANG, Ing-Jer HUANG, "HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2100-2108, August 2010, doi: 10.1587/transinf.E93.D.2100.
Abstract: Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level or chip-level. To overcome the shortage, we propose a rule-based synthesizable AMBA AHB on-chip bus protocol checker, which contains 73 related AHB on-chip bus protocol rules to check AHB bus signal behaviors, and two corresponding verification mechanisms: an error reference table (ERT) and a windowed trace buffer, to shorten verification time.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2100/_p
부
@ARTICLE{e93-d_8_2100,
author={Liang-Bi CHEN, Jiun-Cheng JU, Chien-Chou WANG, Ing-Jer HUANG, },
journal={IEICE TRANSACTIONS on Information},
title={HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms},
year={2010},
volume={E93-D},
number={8},
pages={2100-2108},
abstract={Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level or chip-level. To overcome the shortage, we propose a rule-based synthesizable AMBA AHB on-chip bus protocol checker, which contains 73 related AHB on-chip bus protocol rules to check AHB bus signal behaviors, and two corresponding verification mechanisms: an error reference table (ERT) and a windowed trace buffer, to shorten verification time.},
keywords={},
doi={10.1587/transinf.E93.D.2100},
ISSN={1745-1361},
month={August},}
부
TY - JOUR
TI - HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms
T2 - IEICE TRANSACTIONS on Information
SP - 2100
EP - 2108
AU - Liang-Bi CHEN
AU - Jiun-Cheng JU
AU - Chien-Chou WANG
AU - Ing-Jer HUANG
PY - 2010
DO - 10.1587/transinf.E93.D.2100
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2010
AB - Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level or chip-level. To overcome the shortage, we propose a rule-based synthesizable AMBA AHB on-chip bus protocol checker, which contains 73 related AHB on-chip bus protocol rules to check AHB bus signal behaviors, and two corresponding verification mechanisms: an error reference table (ERT) and a windowed trace buffer, to shorten verification time.
ER -