The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
DPGA(동적 프로그래밍 가능 게이트 어레이)는 기존 FPGA(필드 프로그래밍 가능 게이트 어레이)보다 공간 효율적인 구현을 제공합니다. 일반적인 DPGA 아키텍처 중 하나는 다중 컨텍스트 아키텍처입니다. 다중 컨텍스트 아키텍처를 기반으로 하는 DPGA는 컨텍스트 간 빠른 전환을 구현하는 MC-FPGA(Multi-Context FPGA)입니다. 기존 SRAM 기반 MC-FPGA의 문제점은 구성 메모리 비트 수가 많아 면적이 넓고 대기 전력 소모가 크다는 점이다. 더욱이 SRAM 기반의 다중 상황 FPGA는 휘발성이기 때문에 대기전력 절감을 위한 power-gating 구현이 어렵다. 이 논문은 다중 값 임계값 함수와 비휘발성 다중 값 저장을 병합하는 강유전성 커패시터 기능 패스 게이트를 기반으로 하는 MC-FPGA를 위한 공간 효율적인 비휘발성 다중 컨텍스트 스위치 블록 아키텍처를 제시합니다. 0.35가지 상황에 대한 테스트 칩은 0.60μm-CMOS/63μm-강유전체 커패시터 공정으로 제작되었습니다. 제안된 다중 컨텍스트 스위치 블록의 트랜지스터 수는 SRAM 기반 스위치 블록에 비해 XNUMX%로 감소된다.
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Shota ISHIHARA, Noriaki IDOBATA, Masanori HARIYAMA, Michitaka KAMEYAMA, "A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2134-2144, August 2010, doi: 10.1587/transinf.E93.D.2134.
Abstract: Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2134/_p
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@ARTICLE{e93-d_8_2134,
author={Shota ISHIHARA, Noriaki IDOBATA, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Information},
title={A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals},
year={2010},
volume={E93-D},
number={8},
pages={2134-2144},
abstract={Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.},
keywords={},
doi={10.1587/transinf.E93.D.2134},
ISSN={1745-1361},
month={August},}
부
TY - JOUR
TI - A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals
T2 - IEICE TRANSACTIONS on Information
SP - 2134
EP - 2144
AU - Shota ISHIHARA
AU - Noriaki IDOBATA
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2010
DO - 10.1587/transinf.E93.D.2134
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2010
AB - Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.
ER -