The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 임베디드 시스템 애플리케이션을 위한 저전력 코드를 생성하는 효율적인 명령어 스케줄링 알고리즘을 제시합니다. 제안하는 알고리즘에서는 저전력 코드 생성을 위해 재정렬과 재코딩을 동시에 적용한다. 명령 시퀀스를 적절하게 재정렬하면 명령 기록의 효율성이 높아집니다. 제안하는 알고리즘은 시스템이 유지하고 있는 무작위로 생성된 스케줄들 중에서 코드 시퀀스를 선택하여 기본 블록 단위로 프로그램 코드를 구성한다. 제안하는 알고리즘은 응용 프로그램을 구성하는 기본 블록 각각에 대해 무작위 스케줄을 생성함으로써 각 명령어 필드에 대한 히스토그램 그래프를 구성하여 명령어 시퀀스를 재정렬하여 얻을 수 있는 성능 지수를 추정한다. 추가 최적화를 위해 시스템은 생성된 코드에 대해 시뮬레이션된 어닐링을 수행합니다. 벤치마크 프로그램에 대한 실험 결과, 제안된 알고리즘으로 생성된 코드는 명령어 기록 이전에 리스트 스케줄링을 수행한 기존 알고리즘에 비해 평균 37.2% 적은 전력을 소모하는 것으로 나타났다.
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부
Sung-Rae LEE, Ser-Hoon LEE, Sun-Young HWANG, "A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2162-2171, August 2010, doi: 10.1587/transinf.E93.D.2162.
Abstract: This paper presents an efficient instruction scheduling algorithm which generates low-power codes for embedded system applications. Reordering and recoding are concurrently applied for low-power code generation in the proposed algorithm. By appropriate reordering of instruction sequences, the efficiency of instruction recoding is increased. The proposed algorithm constructs program codes on a basic-block basis by selecting a code sequence from among the schedules generated randomly and maintained by the system. By generating random schedules for each of the basic blocks constituting an application program, the proposed algorithm constructs a histogram graph for each of the instruction fields to estimate the figure-of-merits achievable by reordering instruction sequences. For further optimization, the system performs simulated annealing on the generated code. Experimental results for benchmark programs show that the codes generated by the proposed algorithm consume 37.2% less power on average when compared to the previous algorithm which performs list scheduling prior to instruction recoding.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2162/_p
부
@ARTICLE{e93-d_8_2162,
author={Sung-Rae LEE, Ser-Hoon LEE, Sun-Young HWANG, },
journal={IEICE TRANSACTIONS on Information},
title={A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems},
year={2010},
volume={E93-D},
number={8},
pages={2162-2171},
abstract={This paper presents an efficient instruction scheduling algorithm which generates low-power codes for embedded system applications. Reordering and recoding are concurrently applied for low-power code generation in the proposed algorithm. By appropriate reordering of instruction sequences, the efficiency of instruction recoding is increased. The proposed algorithm constructs program codes on a basic-block basis by selecting a code sequence from among the schedules generated randomly and maintained by the system. By generating random schedules for each of the basic blocks constituting an application program, the proposed algorithm constructs a histogram graph for each of the instruction fields to estimate the figure-of-merits achievable by reordering instruction sequences. For further optimization, the system performs simulated annealing on the generated code. Experimental results for benchmark programs show that the codes generated by the proposed algorithm consume 37.2% less power on average when compared to the previous algorithm which performs list scheduling prior to instruction recoding.},
keywords={},
doi={10.1587/transinf.E93.D.2162},
ISSN={1745-1361},
month={August},}
부
TY - JOUR
TI - A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems
T2 - IEICE TRANSACTIONS on Information
SP - 2162
EP - 2171
AU - Sung-Rae LEE
AU - Ser-Hoon LEE
AU - Sun-Young HWANG
PY - 2010
DO - 10.1587/transinf.E93.D.2162
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2010
AB - This paper presents an efficient instruction scheduling algorithm which generates low-power codes for embedded system applications. Reordering and recoding are concurrently applied for low-power code generation in the proposed algorithm. By appropriate reordering of instruction sequences, the efficiency of instruction recoding is increased. The proposed algorithm constructs program codes on a basic-block basis by selecting a code sequence from among the schedules generated randomly and maintained by the system. By generating random schedules for each of the basic blocks constituting an application program, the proposed algorithm constructs a histogram graph for each of the instruction fields to estimate the figure-of-merits achievable by reordering instruction sequences. For further optimization, the system performs simulated annealing on the generated code. Experimental results for benchmark programs show that the codes generated by the proposed algorithm consume 37.2% less power on average when compared to the previous algorithm which performs list scheduling prior to instruction recoding.
ER -