The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
컴퓨터 메모리 시스템 성능을 개선하기 위한 리소스 무기고에서 지난 몇 년 동안 예측기의 역할이 점점 더 커지고 있습니다. 캐시나 주 메모리에 액세스할 때 대기 시간을 숨길 수 있습니다. 이전 연구에서 우리는 열린 DRAM 행을 닫을 뿐만 아니라 다음 열이 열릴 행도 예측하는 예측기를 갖춘 DDR SDRAM 컨트롤러를 제안했습니다. 이 문서에서는 예측 변수를 더욱 개선하여 최신 유형의 DRAM 메모리인 DDR3 SDRAM에 동일한 기술을 시도할 수 있는 가능성을 탐구합니다.
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Vladimir V. STANKOVIC, Nebojsa Z. MILENKOVIC, "DDR3 SDRAM with a Complete Predictor" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 9, pp. 2635-2638, September 2010, doi: 10.1587/transinf.E93.D.2635.
Abstract: In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They enable hiding the latencies when accessing cache or main memory. In our previous work we proposed a DDR SDRAM controller with predictors that not only close the opened DRAM row but also predict the next row to be opened. In this paper we explore the possibilities of trying the same techniques on the latest type of DRAM memory, DDR3 SDRAM, with further improvements of the predictors.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2635/_p
부
@ARTICLE{e93-d_9_2635,
author={Vladimir V. STANKOVIC, Nebojsa Z. MILENKOVIC, },
journal={IEICE TRANSACTIONS on Information},
title={DDR3 SDRAM with a Complete Predictor},
year={2010},
volume={E93-D},
number={9},
pages={2635-2638},
abstract={In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They enable hiding the latencies when accessing cache or main memory. In our previous work we proposed a DDR SDRAM controller with predictors that not only close the opened DRAM row but also predict the next row to be opened. In this paper we explore the possibilities of trying the same techniques on the latest type of DRAM memory, DDR3 SDRAM, with further improvements of the predictors.},
keywords={},
doi={10.1587/transinf.E93.D.2635},
ISSN={1745-1361},
month={September},}
부
TY - JOUR
TI - DDR3 SDRAM with a Complete Predictor
T2 - IEICE TRANSACTIONS on Information
SP - 2635
EP - 2638
AU - Vladimir V. STANKOVIC
AU - Nebojsa Z. MILENKOVIC
PY - 2010
DO - 10.1587/transinf.E93.D.2635
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2010
AB - In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They enable hiding the latencies when accessing cache or main memory. In our previous work we proposed a DDR SDRAM controller with predictors that not only close the opened DRAM row but also predict the next row to be opened. In this paper we explore the possibilities of trying the same techniques on the latest type of DRAM memory, DDR3 SDRAM, with further improvements of the predictors.
ER -