The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
순차 회로의 테스트 패턴 생성이 어렵기 때문에 여러 DFT(테스트 가능성을 위한 설계) 접근 방식이 제안되었습니다. 오늘날의 더욱 복잡한 칩의 요구 사항을 충족하려면 이러한 현재 접근 방식을 개선해야 합니다. 본 논문에서는 기존 기능 요소와 테스트 경로를 최적으로 활용하는 회로의 상위 수준 설명에 적용할 수 있는 새로운 DFT 방법을 소개합니다. F-스캔이라고 하는 이 기술은 결함 적용 범위를 손상시키지 않으면서 테스트로 인한 하드웨어 오버헤드를 효과적으로 줄입니다. 시험 신청 시간도 최소한으로 유지됩니다. F-스캔과 게이트 레벨 풀 스캔 설계의 성능 비교는 실험 결과를 통해 보여줍니다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Marie Engelene J. OBIEN, Satoshi OHTAKE, Hideo FUJIWARA, "F-Scan: A DFT Method for Functional Scan at RTL" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 1, pp. 104-113, January 2011, doi: 10.1587/transinf.E94.D.104.
Abstract: Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.104/_p
부
@ARTICLE{e94-d_1_104,
author={Marie Engelene J. OBIEN, Satoshi OHTAKE, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={F-Scan: A DFT Method for Functional Scan at RTL},
year={2011},
volume={E94-D},
number={1},
pages={104-113},
abstract={Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.},
keywords={},
doi={10.1587/transinf.E94.D.104},
ISSN={1745-1361},
month={January},}
부
TY - JOUR
TI - F-Scan: A DFT Method for Functional Scan at RTL
T2 - IEICE TRANSACTIONS on Information
SP - 104
EP - 113
AU - Marie Engelene J. OBIEN
AU - Satoshi OHTAKE
AU - Hideo FUJIWARA
PY - 2011
DO - 10.1587/transinf.E94.D.104
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2011
AB - Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.
ER -