The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 논문은 모듈러스 세트 {2를 기반으로 효율적인 역변환기를 설계하기 위한 일반적인 아키텍처를 제시합니다.α, 22β+1- 1, 2β-1}, 여기서 β < α ≤ 2β는 혼합 기수 변환(MRC) 알고리즘의 병렬 구현을 사용합니다. 모듈러스 세트 {2α, 22β+1- 1, 2β-1}은 모듈로(2k+1)-잔수 체계(RNS)에 대한 효율적인 산술 단위를 생성할 수 있는 유형입니다. 필요한 동적 범위(DR)를 제공하고 모듈러스 비트 폭 간의 원하는 평형을 조정하기 위해 α 및 β 값을 선택할 수 있습니다. 제안된 모듈러스 집합의 간단한 곱셈 역과 새로운 기술을 사용하여 변환 방정식을 단순화함으로써 다양한 DR을 지원하는 데 사용할 수 있는 복잡성이 낮고 성능이 뛰어난 일반 역변환 아키텍처가 탄생했습니다. 또한 현재 5n비트 DR 모듈러스 세트의 중요성으로 인해 모듈러스 세트 {2도 도입했습니다.2n, 22n+1- 1, 2n-1}은 일반 집합 {2의 특별한 경우입니다.α, 22β+1- 1, 2β-1}, 여기서 α=2n이고 β=n입니다. 이 특수 세트용 변환기는 5n비트 DR 모듈 세트 {2용으로 설계된 가장 빠른 최첨단 역방향 변환기보다 더 빠른 속도를 제공하는 제시된 일반 아키텍처에서 파생됩니다.2n, 22n+1- 1, 2n-1}. 또한 이론적 및 FPGA 구현 결과는 제안된 모듈러스 세트 {2에 대한 역변환기2n, 22n+1- 1, 2n-1} 유사한 DR을 사용하는 다른 작업에 비해 하드웨어 요구 사항이 적고 변환 지연이 크게 개선됩니다.
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Keivan NAVI, Mohammad ESMAEILDOUST, Amir SABBAGH MOLAHOSSEINI, "A General Reverse Converter Architecture with Low Complexity and High Performance" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 2, pp. 264-273, February 2011, doi: 10.1587/transinf.E94.D.264.
Abstract: This paper presents a general architecture for designing efficient reverse converters based on the moduli set {2α, 22β+1-1, 2β-1}, where β < α ≤ 2β, by using a parallel implementation of mixed-radix conversion (MRC) algorithm. The moduli set {2α, 22β+1-1, 2β-1} is free from modulo (2k+1)-type which can result in an efficient arithmetic unit for residue number system (RNS). The values of α and β can be selected to provide the required dynamic range (DR) and also to adjust the desired equilibrium between moduli bit-width. The simple multiplicative inverses of the proposed moduli set and also using novel techniques to simplify conversion equations lead to a low-complexity and high-performance general reverse converter architecture that can be used to support different DRs. Moreover, due to the current importance of the 5n-bit DR moduli sets, we also introduced the moduli set {22n, 22n+1-1, 2n-1} which is a special case of the general set {2α, 22β+1-1, 2β-1}, where α=2n and β=n. The converter for this special set is derived from the presented general architecture with higher speed than the fastest state-of-the-art reverse converter which has been designed for the 5n-bit DR moduli set {22n, 22n+1-1, 2n-1}. Furthermore, theoretical and FPGA implementation results show that the proposed reverse converter for moduli set {22n, 22n+1-1, 2n-1} results in considerable improvement in conversion delay with less hardware requirements compared to other works with similar DR.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.264/_p
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@ARTICLE{e94-d_2_264,
author={Keivan NAVI, Mohammad ESMAEILDOUST, Amir SABBAGH MOLAHOSSEINI, },
journal={IEICE TRANSACTIONS on Information},
title={A General Reverse Converter Architecture with Low Complexity and High Performance},
year={2011},
volume={E94-D},
number={2},
pages={264-273},
abstract={This paper presents a general architecture for designing efficient reverse converters based on the moduli set {2α, 22β+1-1, 2β-1}, where β < α ≤ 2β, by using a parallel implementation of mixed-radix conversion (MRC) algorithm. The moduli set {2α, 22β+1-1, 2β-1} is free from modulo (2k+1)-type which can result in an efficient arithmetic unit for residue number system (RNS). The values of α and β can be selected to provide the required dynamic range (DR) and also to adjust the desired equilibrium between moduli bit-width. The simple multiplicative inverses of the proposed moduli set and also using novel techniques to simplify conversion equations lead to a low-complexity and high-performance general reverse converter architecture that can be used to support different DRs. Moreover, due to the current importance of the 5n-bit DR moduli sets, we also introduced the moduli set {22n, 22n+1-1, 2n-1} which is a special case of the general set {2α, 22β+1-1, 2β-1}, where α=2n and β=n. The converter for this special set is derived from the presented general architecture with higher speed than the fastest state-of-the-art reverse converter which has been designed for the 5n-bit DR moduli set {22n, 22n+1-1, 2n-1}. Furthermore, theoretical and FPGA implementation results show that the proposed reverse converter for moduli set {22n, 22n+1-1, 2n-1} results in considerable improvement in conversion delay with less hardware requirements compared to other works with similar DR.},
keywords={},
doi={10.1587/transinf.E94.D.264},
ISSN={1745-1361},
month={February},}
부
TY - JOUR
TI - A General Reverse Converter Architecture with Low Complexity and High Performance
T2 - IEICE TRANSACTIONS on Information
SP - 264
EP - 273
AU - Keivan NAVI
AU - Mohammad ESMAEILDOUST
AU - Amir SABBAGH MOLAHOSSEINI
PY - 2011
DO - 10.1587/transinf.E94.D.264
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2011
AB - This paper presents a general architecture for designing efficient reverse converters based on the moduli set {2α, 22β+1-1, 2β-1}, where β < α ≤ 2β, by using a parallel implementation of mixed-radix conversion (MRC) algorithm. The moduli set {2α, 22β+1-1, 2β-1} is free from modulo (2k+1)-type which can result in an efficient arithmetic unit for residue number system (RNS). The values of α and β can be selected to provide the required dynamic range (DR) and also to adjust the desired equilibrium between moduli bit-width. The simple multiplicative inverses of the proposed moduli set and also using novel techniques to simplify conversion equations lead to a low-complexity and high-performance general reverse converter architecture that can be used to support different DRs. Moreover, due to the current importance of the 5n-bit DR moduli sets, we also introduced the moduli set {22n, 22n+1-1, 2n-1} which is a special case of the general set {2α, 22β+1-1, 2β-1}, where α=2n and β=n. The converter for this special set is derived from the presented general architecture with higher speed than the fastest state-of-the-art reverse converter which has been designed for the 5n-bit DR moduli set {22n, 22n+1-1, 2n-1}. Furthermore, theoretical and FPGA implementation results show that the proposed reverse converter for moduli set {22n, 22n+1-1, 2n-1} results in considerable improvement in conversion delay with less hardware requirements compared to other works with similar DR.
ER -